From: David Miller <davem@davemloft.net>
To: madalin.bucur@oss.nxp.com
Cc: netdev@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com,
devicetree@vger.kernel.org
Subject: Re: [PATCH net 0/3] net: fsl/fman: address erratum A011043
Date: Thu, 23 Jan 2020 21:17:33 +0100 (CET) [thread overview]
Message-ID: <20200123.211733.1373762254655962948.davem@davemloft.net> (raw)
In-Reply-To: <1579699229-5948-1-git-send-email-madalin.bucur@oss.nxp.com>
From: Madalin Bucur <madalin.bucur@oss.nxp.com>
Date: Wed, 22 Jan 2020 15:20:26 +0200
> This addresses a HW erratum on some QorIQ DPAA devices.
>
> MDIO reads to internal PCS registers may result in having
> the MDIO_CFG[MDIO_RD_ER] bit set, even when there is no
> error and read data (MDIO_DATA[MDIO_DATA]) is correct.
> Software may get false read error when reading internal
> PCS registers through MDIO. As a workaround, all internal
> MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.
> When the issue was present, one could see such errors
> during boot:
>
> mdio_bus ffe4e5000: Error while reading PHY0 reg at 3.3
Series applied.
next prev parent reply other threads:[~2020-01-23 20:17 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-22 13:20 [PATCH net 0/3] net: fsl/fman: address erratum A011043 Madalin Bucur
2020-01-22 13:20 ` [PATCH net 1/3] dt-bindings: net: add fsl,erratum-a011043 Madalin Bucur
2020-01-22 13:20 ` [PATCH net 2/3] powerpc/fsl/dts: " Madalin Bucur
2020-01-22 13:20 ` [PATCH net 3/3] net/fsl: treat fsl,erratum-a011043 Madalin Bucur
2020-01-23 20:17 ` David Miller [this message]
2020-01-23 21:09 ` [PATCH net 0/3] net: fsl/fman: address erratum A011043 Florian Fainelli
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