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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id n64sm4379460otn.35.2020.01.27.09.53.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jan 2020 09:53:35 -0800 (PST) Received: (nullmailer pid 30258 invoked by uid 1000); Mon, 27 Jan 2020 17:53:34 -0000 Date: Mon, 27 Jan 2020 11:53:34 -0600 From: Rob Herring To: Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, gregkh@linuxfoundation.org, jackp@codeaurora.org, balbi@kernel.org, bjorn.andersson@linaro.org, linux-kernel@vger.kernel.org, Sriharsha Allenki , Anu Ramanathan , Shawn Guo , Andy Gross , Kishon Vijay Abraham I , Mark Rutland , Jorge Ramirez-Ortiz , devicetree@vger.kernel.org Subject: Re: [PATCH v3 02/19] dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding Message-ID: <20200127175334.GA12315@bogus> References: <20200122185610.131930-1-bryan.odonoghue@linaro.org> <20200122185610.131930-3-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200122185610.131930-3-bryan.odonoghue@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Jan 22, 2020 at 06:55:53PM +0000, Bryan O'Donoghue wrote: > From: Sriharsha Allenki > > Adds bindings for QCS404 USB PHY supporting Low-Speed, Full-Speed and > Hi-Speed USB connectivity on Qualcomm chipsets. > > [bod: Converted to YAML. Changed name dropping snps, 28nm components] > > Signed-off-by: Sriharsha Allenki > Signed-off-by: Anu Ramanathan > Signed-off-by: Bjorn Andersson > Signed-off-by: Shawn Guo > Cc: Andy Gross > Cc: Bjorn Andersson > Cc: Kishon Vijay Abraham I > Cc: Rob Herring > Cc: Mark Rutland > Cc: Jorge Ramirez-Ortiz > Cc: linux-arm-msm@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: devicetree@vger.kernel.org > Signed-off-by: Bryan O'Donoghue > --- > .../bindings/phy/qcom,qcs404-usb-hs.yaml | 77 +++++++++++++++++++ > 1 file changed, 77 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml > new file mode 100644 > index 000000000000..d71beb822ae2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,qcs404-usb-hs.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/phy/qcom,qcs404-usb-hs.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Qualcomm Synopsys QCS-404 High-Speed PHY > + > +maintainers: > + - Bryan O'Donoghue > + > +description: | > + Qualcomm QCS-404 Low-Speed, Full-Speed, Hi-Speed USB PHY > + > +properties: > + compatible: > + enum: > + - qcom,qcs404-usb-hsphy > + > + reg: > + maxItems: 1 > + description: USB PHY base address and length of the register map. > + > + "#phy-cells": > + const: 0 > + description: Should be 0. See phy/phy-bindings.txt for details. > + > + clocks: > + minItems: 3 > + maxItems: 3 > + description: phandles to rpmcc ref clock, PHY AHB clock, rentention clock. > + > + clock-names: > + items: > + - const: ref > + - const: phy > + - const: sleep > + > + resets: > + items: > + - description: PHY core reset > + - description: POR reset > + > + reset-names: > + items: > + - const: phy > + - const: por > + > + vdd-supply: > + maxItems: 1 Supplies are always 1 entry, so drop this. > + description: phandle to the regulator VDD supply node. > + > + vdda1p8-supply: > + maxItems: 1 > + description: phandle to the regulator 1.8V supply node. > + > + vdda3p3-supply: > + maxItems: 1 > + description: phandle to the regulator 3.3V supply node. No required properties? Add: additionalProperties: false > + > +examples: > + - | > + #include > + #include > + usb2_phy_prim: phy@7a000 { > + compatible = "qcom,qcs404-usb-hsphy"; > + reg = <0x0007a000 0x200>; > + #phy-cells = <0>; > + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, > + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, > + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; > + clock-names = "ref", "phy", "sleep"; > + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, > + <&gcc GCC_USB2A_PHY_BCR>; > + reset-names = "phy", "por"; > + }; > +... > -- > 2.25.0 >