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In-Reply-To: <20191213083402.35678-2-wen.he_1@nxp.com>
References: <20191213083402.35678-1-wen.he_1@nxp.com> <20191213083402.35678-2-wen.he_1@nxp.com>
Subject: Re: [v12 2/2] clk: ls1028a: Add clock driver for Display output interface
To:     Li Yang <leoyang.li@nxp.com>, Mark Rutland <mark.rutland@arm.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Michael Walle <michael@walle.cc>,
        Rob Herring <robh+dt@kernel.org>, Wen He <wen.he_1@nxp.com>,
        devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Wen He <wen.he_1@nxp.com>
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Date:   Thu, 30 Jan 2020 16:32:07 -0800
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Quoting Wen He (2019-12-13 00:34:02)
> Add clock driver for QorIQ LS1028A Display output interfaces(LCD, DPHY),
> as implemented in TSMC CLN28HPM PLL, this PLL supports the programmable
> integer division and range of the display output pixel clock's 27-594MHz.
>=20
> Signed-off-by: Wen He <wen.he_1@nxp.com>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---

Applied to clk-next