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Mon, 10 Feb 2020 10:55:01 -0800 (PST) Received: from kozik-lap ([194.230.155.125]) by smtp.googlemail.com with ESMTPSA id j21sm74756eds.8.2020.02.10.10.54.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 Feb 2020 10:55:00 -0800 (PST) Date: Mon, 10 Feb 2020 19:54:58 +0100 From: Krzysztof Kozlowski To: Anand Moon Cc: Linux USB Mailing List , devicetree , linux-arm-kernel , Greg Kroah-Hartman , Rob Herring , Mark Rutland , Felipe Balbi , Marek Szyprowski , Bartlomiej Zolnierkiewicz , linux-samsung-soc@vger.kernel.org, Linux Kernel Subject: Re: [PATCHv3 2/3] ARM: dts: exynos: Add missing usbdrd3 suspend clk Message-ID: <20200210185458.GA16433@kozik-lap> References: <20200210105108.1128-1-linux.amoon@gmail.com> <20200210105108.1128-3-linux.amoon@gmail.com> <20200210135008.GA2163@pi3> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Feb 10, 2020 at 10:43:45PM +0530, Anand Moon wrote: > Hi Krzysztof, > > Thanks for your review comments. > > On Mon, 10 Feb 2020 at 19:20, Krzysztof Kozlowski wrote: > > > > On Mon, Feb 10, 2020 at 10:51:07AM +0000, Anand Moon wrote: > > > This patch adds new combatible strings for USBDRD3 > > > for adding missing suspend clk, exynos5422 usbdrd3 > > > support two clk USBD300 and SCLK_USBD300, so add missing > > > suspemd_clk for Exynos542x DWC3 nodes. > > > > > > Signed-off-by: Anand Moon > > > --- > > > arch/arm/boot/dts/exynos5420.dtsi | 8 ++++---- > > > arch/arm/boot/dts/exynos54xx.dtsi | 4 ++-- > > > 2 files changed, 6 insertions(+), 6 deletions(-) > > > > > > diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi > > > index b672080e7469..bd505256a223 100644 > > > --- a/arch/arm/boot/dts/exynos5420.dtsi > > > +++ b/arch/arm/boot/dts/exynos5420.dtsi > > > @@ -1372,8 +1372,8 @@ &trng { > > > }; > > > > > > &usbdrd3_0 { > > > - clocks = <&clock CLK_USBD300>; > > > - clock-names = "usbdrd30"; > > > + clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>; > > > + clock-names = "usbdrd30", "usbdrd30_susp_clk"; > > > }; > > > > > > &usbdrd_phy0 { > > > @@ -1383,8 +1383,8 @@ &usbdrd_phy0 { > > > }; > > > > > > &usbdrd3_1 { > > > - clocks = <&clock CLK_USBD301>; > > > - clock-names = "usbdrd30"; > > > + clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>; > > > + clock-names = "usbdrd30", "usbdrd30_susp_clk"; > > > }; > > > > > > &usbdrd_dwc3_1 { > > > diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi > > > index 8aa5117e58ce..0aac6255de5d 100644 > > > --- a/arch/arm/boot/dts/exynos54xx.dtsi > > > +++ b/arch/arm/boot/dts/exynos54xx.dtsi > > > @@ -143,7 +143,7 @@ hsi2c_7: i2c@12cd0000 { > > > }; > > > > > > usbdrd3_0: usb3-0 { > > > - compatible = "samsung,exynos5250-dwusb3"; > > > + compatible = "samsung,exynos5420-dwusb3"; > > > #address-cells = <1>; > > > #size-cells = <1>; > > > ranges; > > > @@ -165,7 +165,7 @@ usbdrd_phy0: phy@12100000 { > > > }; > > > > > > usbdrd3_1: usb3-1 { > > > - compatible = "samsung,exynos5250-dwusb3"; > > > + compatible = "samsung,exynos5420-dwusb3"; > > > > This affects also Exynos5410 but you do not add new clock there. > > > > Best regards, > > Krzysztof > > > > Ok I will update this Exynos5410 dts. > > Is samsung,exynos54xx-dwusb3 is valid compatible string > for both the SoC. The compatible should not be wildcard so keep it as samsung,exynos5420-dwusb3. Best regards, Krzysztof