From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8A5FC3B1B7 for ; Fri, 14 Feb 2020 18:13:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A121D2187F for ; Fri, 14 Feb 2020 18:13:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581703990; bh=eBLejqYBNJZKgtBkhP+tpe58QdQ8fptkUqSNNoPg7is=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=r+aPnf6Mrh+BQE5r/RP7l3HOfGlA9lRTj8RSvgX+Qe5TJHHjZuLu8DgEjAEegYYiD zCfqLqLGSlrcZuVw1sW910Wbrn+dnkuVoBUtetx41eqLse3Pm3DUZFi5R/bLt5cVnW BrgQhsCLFlkzeIVikcq1MSGKe9W/mRVKBVs9jhvw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731086AbgBNPwy (ORCPT ); Fri, 14 Feb 2020 10:52:54 -0500 Received: from mail.kernel.org ([198.145.29.99]:59908 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731083AbgBNPwy (ORCPT ); Fri, 14 Feb 2020 10:52:54 -0500 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A097224681; Fri, 14 Feb 2020 15:52:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581695573; bh=eBLejqYBNJZKgtBkhP+tpe58QdQ8fptkUqSNNoPg7is=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=H29JSwIxlfaC3Wgc1yyCpzZCSGwRuQ7CFUwnRZK6VcIx0E95VI1bImL/A71ZUjA4h yXMMKOjrOx6B9kFvlIlZ540wscovugFjQSV8O+4ZHjz+5e3tIHRz+qN7lzCkjARzRL MTPxbrZO6u1F7SimU1zhxnxfPQOrf8hegb3Es8cs= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Andre Przywara , Maxime Ripard , Sasha Levin , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH AUTOSEL 5.5 184/542] arm64: dts: allwinner: H5: Add PMU node Date: Fri, 14 Feb 2020 10:42:56 -0500 Message-Id: <20200214154854.6746-184-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214154854.6746-1-sashal@kernel.org> References: <20200214154854.6746-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Andre Przywara [ Upstream commit c35a516a46187c8eeb7a56c64505ec6f7e22a0c7 ] Add the Performance Monitoring Unit (PMU) device tree node to the H5 .dtsi, which tells DT users which interrupts are triggered by PMU overflow events on each core. As with the A64, the interrupt numbers from the manual were wrong (off by 4), the actual SPI IDs have been gathered in U-Boot, and were verified with perf in Linux. Tested with perf record and taskset on an OrangePi PC2. Signed-off-by: Andre Przywara Signed-off-by: Maxime Ripard Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index e92c4de5bf3b4..7c775a918a4e7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -54,21 +54,21 @@ enable-method = "psci"; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <1>; enable-method = "psci"; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <2>; enable-method = "psci"; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <3>; @@ -76,6 +76,16 @@ }; }; + pmu { + compatible = "arm,cortex-a53-pmu", + "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + psci { compatible = "arm,psci-0.2"; method = "smc"; -- 2.20.1