[PATCH devicetree 0/4] DT bindings for Felix DSA switch on LS1028A

[PATCH devicetree 0/4] DT bindings for Felix DSA switch on LS1028A

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

This series officializes the device tree bindings for the embedded
Ethernet switch on NXP LS1028A (and for the reference design board).
The driver has been in the tree since v5.4-rc6.

Claudiu Manoil (2):
  arm64: dts: fsl: ls1028a: add node for Felix switch
  arm64: dts: fsl: ls1028a: enable switch PHYs on RDB

Vladimir Oltean (2):
  arm64: dts: fsl: ls1028a: delete extraneous #interrupt-cells for ENETC
    RCIE
  dt-bindings: net: dsa: ocelot: document the vsc9959 core

 .../devicetree/bindings/net/dsa/ocelot.txt    | 97 +++++++++++++++++++
 .../boot/dts/freescale/fsl-ls1028a-rdb.dts    | 51 ++++++++++
 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 85 +++++++++++++++-
 3 files changed, 231 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/dsa/ocelot.txt

-- 
2.17.1

[PATCH devicetree 1/4] arm64: dts: fsl: ls1028a: delete extraneous #interrupt-cells for ENETC RCIE

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

This specifier overrides the interrupt specifier with 3 cells from gic
(/interrupt-controller@6000000), but in fact ENETC is not an interrupt
controller, so the property is bogus.

Interrupts used by the children of the ENETC RCIE must use the full
3-cell specifier required by the GIC.

Fixes: 927d7f857542 ("arm64: dts: fsl: ls1028a: Add PCI IERC node and ENETC endpoints")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 0bf375ec959b..dfead691e509 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -683,7 +683,6 @@
 			reg = <0x01 0xf0000000 0x0 0x100000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
-			#interrupt-cells = <1>;
 			msi-parent = <&its>;
 			device_type = "pci";
 			bus-range = <0x0 0x0>;
-- 
2.17.1

[PATCH devicetree 2/4] dt-bindings: net: dsa: ocelot: document the vsc9959 core

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

This patch adds the required documentation for the embedded L2 switch
inside the NXP LS1028A chip.

I've submitted it in the legacy format instead of yaml schema, because
DSA itself has not yet been converted to yaml, and this driver defines
no custom bindings.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 .../devicetree/bindings/net/dsa/ocelot.txt    | 97 +++++++++++++++++++
 1 file changed, 97 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/dsa/ocelot.txt

diff --git a/Documentation/devicetree/bindings/net/dsa/ocelot.txt b/Documentation/devicetree/bindings/net/dsa/ocelot.txt
new file mode 100644
index 000000000000..6afd677c6ac0
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/ocelot.txt
@@ -0,0 +1,97 @@
+Microchip Ocelot switch driver family
+=====================================
+
+Felix
+-----
+
+The VSC9959 core is currently the only switch supported by the driver, and is
+found in the NXP LS1028A. It is a PCI device, part of the larger ENETC root
+complex. As a result, the ethernet-switch node is a sub-node of the PCIe root
+complex node and its "reg" property conforms to the parent node bindings:
+
+* reg: Specifies PCIe Device Number and Function Number of the endpoint device,
+  in this case for the Ethernet L2Switch it is PF5 (of device 0, bus 0).
+
+It does not require a "compatible" string.
+
+The interrupt line is used to signal availability of PTP TX timestamps and for
+TSN frame preemption.
+
+For the external switch ports, depending on board configuration, "phy-mode" and
+"phy-handle" are populated by board specific device tree instances. Ports 4 and
+5 are fixed as internal ports in the NXP LS1028A instantiation.
+
+Any port can be disabled, but the CPU port should be kept enabled.
+
+The CPU port property ("ethernet"), which is assigned by default to the 2.5Gbps
+port@4, can be moved to the 1Gbps port@5, depending on the specific use case.
+DSA tagging is supported on a single port at a time.
+
+For the rest of the device tree binding definitions, which are standard DSA and
+PCI, refer to the following documents:
+
+Documentation/devicetree/bindings/net/dsa/dsa.txt
+Documentation/devicetree/bindings/pci/pci.txt
+
+Example:
+
+&soc {
+	pcie@1f0000000 { /* Integrated Endpoint Root Complex */
+		ethernet-switch@0,5 {
+			reg = <0x000500 0 0 0 0>;
+			/* IEP INT_B */
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				/* External ports */
+				port@0 {
+					reg = <0>;
+					label = "swp0";
+				};
+
+				port@1 {
+					reg = <1>;
+					label = "swp1";
+				};
+
+				port@2 {
+					reg = <2>;
+					label = "swp2";
+				};
+
+				port@3 {
+					reg = <3>;
+					label = "swp3";
+				};
+
+				/* Internal CPU port */
+				port@4 {
+					reg = <4>;
+					ethernet = <&enetc_port2>;
+					phy-mode = "gmii";
+
+					fixed-link {
+						speed = <2500>;
+						full-duplex;
+					};
+				};
+
+				/* Internal non-CPU port */
+				port@5 {
+					reg = <5>;
+					phy-mode = "gmii";
+					status = "disabled";
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+						pause;
+					};
+				};
+			};
+		};
+	};
+};
-- 
2.17.1

[PATCH devicetree 3/4] arm64: dts: fsl: ls1028a: add node for Felix switch

[Vladimir Oltean]

From: Claudiu Manoil <claudiu.manoil@nxp.com>

Add the switch device node, available on PF5, so that the switch port
sub-nodes (net devices) can be linked to corresponding board specific
phy nodes (external ports) or have their link mode defined (internal
ports).

The switch device features 6 ports, 4 with external links and 2
internally facing to the LS1028A SoC and connected via fixed links to 2
internal ENETC Ethernet controller ports.

Add the corresponding ENETC host port device nodes, mapped to PF2 and
PF6 PCIe functions. Since the switch only supports tagging on one CPU
port, only one port pair (swp4, eno2) is enabled by default and the
other, lower speed, port pair is disabled to prevent the PCI core from
probing them. If enabled, swp5 will be a fixed-link slave port.

DSA tagging can also be moved from the swp4-eno2 2.5G port pair to the
1G swp5-eno3 pair by changing the ethernet = <&enetc_port2> phandle to
<&enetc_port3> and moving it under port5, but in that case enetc_port2
should not be disabled, because it is the hardware owner of the Felix
PCS and disabling its memory would result in access faults in the Felix
DSA driver.

All ports are disabled by default, except one CPU port.

The switch's INTB interrupt line signals:
- PTP timestamp ready in timestamp FIFO
- TSN Frame Preemption

And don't forget to enable the 4MB BAR4 in the root complex ECAM space,
where the switch registers are mapped.

Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 84 ++++++++++++++++++-
 1 file changed, 83 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index dfead691e509..b35679dbcaa7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -700,7 +700,9 @@
 				  /* PF1: VF0-1 BAR0 - non-prefetchable memory */
 				  0x82000000 0x0 0x00000000  0x1 0xf8210000  0x0 0x020000
 				  /* PF1: VF0-1 BAR2 - prefetchable memory */
-				  0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000>;
+				  0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000
+				  /* BAR4 (PF5) - non-prefetchable memory */
+				  0x82000000 0x0 0x00000000  0x1 0xfc000000  0x0 0x400000>;
 
 			enetc_port0: ethernet@0,0 {
 				compatible = "fsl,enetc";
@@ -710,6 +712,18 @@
 				compatible = "fsl,enetc";
 				reg = <0x000100 0 0 0 0>;
 			};
+
+			enetc_port2: ethernet@0,2 {
+				compatible = "fsl,enetc";
+				reg = <0x000200 0 0 0 0>;
+				phy-mode = "gmii";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
 			enetc_mdio_pf3: mdio@0,3 {
 				compatible = "fsl,enetc-mdio";
 				reg = <0x000300 0 0 0 0>;
@@ -722,6 +736,74 @@
 				clocks = <&clockgen 4 0>;
 				little-endian;
 			};
+
+			ethernet-switch@0,5 {
+				reg = <0x000500 0 0 0 0>;
+				/* IEP INT_B */
+				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					/* external ports */
+					mscc_felix_port0: port@0 {
+						reg = <0>;
+						status = "disabled";
+					};
+
+					mscc_felix_port1: port@1 {
+						reg = <1>;
+						status = "disabled";
+					};
+
+					mscc_felix_port2: port@2 {
+						reg = <2>;
+						status = "disabled";
+					};
+
+					mscc_felix_port3: port@3 {
+						reg = <3>;
+						status = "disabled";
+					};
+
+					/* Internal port with DSA tagging */
+					mscc_felix_port4: port@4 {
+						reg = <4>;
+						phy-mode = "gmii";
+						ethernet = <&enetc_port2>;
+
+						fixed-link {
+							speed = <2500>;
+							full-duplex;
+						};
+					};
+
+					/* Internal port without DSA tagging */
+					mscc_felix_port5: port@5 {
+						reg = <5>;
+						phy-mode = "gmii";
+						status = "disabled";
+
+						fixed-link {
+							speed = <1000>;
+							full-duplex;
+						};
+					};
+				};
+			};
+
+			enetc_port3: ethernet@0,6 {
+				compatible = "fsl,enetc";
+				reg = <0x000600 0 0 0 0>;
+				status = "disabled";
+				phy-mode = "gmii";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
 		};
 	};
 
-- 
2.17.1

Re: [PATCH devicetree 3/4] arm64: dts: fsl: ls1028a: add node for Felix switch

[Andrew Lunn]

Hi Vladimir

> +					/* Internal port with DSA tagging */
> +					mscc_felix_port4: port@4 {
> +						reg = <4>;
> +						phy-mode = "gmii";

Is it really using gmii? Often in SoC connections use something else,
and phy-mode = "internal" is more appropriate.

> +						ethernet = <&enetc_port2>;
> +
> +						fixed-link {
> +							speed = <2500>;
> +							full-duplex;
> +						};

gmii and 2500 also don't really go together.

     Andrew

Re: [PATCH devicetree 3/4] arm64: dts: fsl: ls1028a: add node for Felix switch

[Vladimir Oltean]

Hi Andrew,

On Mon, 17 Feb 2020 at 17:29, Andrew Lunn <andrew@lunn.ch> wrote:
>
> Hi Vladimir
>
> > +                                     /* Internal port with DSA tagging */
> > +                                     mscc_felix_port4: port@4 {
> > +                                             reg = <4>;
> > +                                             phy-mode = "gmii";
>
> Is it really using gmii? Often in SoC connections use something else,
> and phy-mode = "internal" is more appropriate.
>

What would be that "something else"? Given that the host port and the
switch are completely different hardware IP blocks, I would assume
that a parallel GMII is what's connecting them, no optimizations done.
Certainly no serializer. But I don't know for sure.
Does it matter, in the end?

> > +                                             ethernet = <&enetc_port2>;
> > +
> > +                                             fixed-link {
> > +                                                     speed = <2500>;
> > +                                                     full-duplex;
> > +                                             };
>
> gmii and 2500 also don't really go together.

Not even if you raise the clock frequency?

>
>      Andrew

Thanks,
-Vladimir

Re: [PATCH devicetree 3/4] arm64: dts: fsl: ls1028a: add node for Felix switch

[Vladimir Oltean]

On Mon, 17 Feb 2020 at 17:33, Vladimir Oltean <olteanv@gmail.com> wrote:
>
> Hi Andrew,
>
> On Mon, 17 Feb 2020 at 17:29, Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > Hi Vladimir
> >
> > > +                                     /* Internal port with DSA tagging */
> > > +                                     mscc_felix_port4: port@4 {
> > > +                                             reg = <4>;
> > > +                                             phy-mode = "gmii";
> >
> > Is it really using gmii? Often in SoC connections use something else,
> > and phy-mode = "internal" is more appropriate.
> >
>
> What would be that "something else"? Given that the host port and the
> switch are completely different hardware IP blocks, I would assume
> that a parallel GMII is what's connecting them, no optimizations done.
> Certainly no serializer. But I don't know for sure.
> Does it matter, in the end?
>

To clarify, the reason I'm asking whether it matters is because I'd
have to modify PHY_INTERFACE_MODE_GMII in
drivers/net/dsa/ocelot/felix_vsc9959.c too, for the internal ports.
Then I'm not sure anymore what tree this device tree patch should go
in through.

> > > +                                             ethernet = <&enetc_port2>;
> > > +
> > > +                                             fixed-link {
> > > +                                                     speed = <2500>;
> > > +                                                     full-duplex;
> > > +                                             };
> >
> > gmii and 2500 also don't really go together.
>
> Not even if you raise the clock frequency?
>
> >
> >      Andrew
>
> Thanks,
> -Vladimir

Re: [PATCH devicetree 3/4] arm64: dts: fsl: ls1028a: add node for Felix switch

[Vladimir Oltean]

Hi Andrew,

On Mon, 17 Feb 2020 at 19:24, Vladimir Oltean <olteanv@gmail.com> wrote:
>
> On Mon, 17 Feb 2020 at 17:33, Vladimir Oltean <olteanv@gmail.com> wrote:
> >
> > Hi Andrew,
> >
> > On Mon, 17 Feb 2020 at 17:29, Andrew Lunn <andrew@lunn.ch> wrote:
> > >
> > > Hi Vladimir
> > >
> > > > +                                     /* Internal port with DSA tagging */
> > > > +                                     mscc_felix_port4: port@4 {
> > > > +                                             reg = <4>;
> > > > +                                             phy-mode = "gmii";
> > >
> > > Is it really using gmii? Often in SoC connections use something else,
> > > and phy-mode = "internal" is more appropriate.
> > >
> >
> > What would be that "something else"? Given that the host port and the
> > switch are completely different hardware IP blocks, I would assume
> > that a parallel GMII is what's connecting them, no optimizations done.
> > Certainly no serializer. But I don't know for sure.
> > Does it matter, in the end?
> >
>
> To clarify, the reason I'm asking whether it matters is because I'd
> have to modify PHY_INTERFACE_MODE_GMII in
> drivers/net/dsa/ocelot/felix_vsc9959.c too, for the internal ports.
> Then I'm not sure anymore what tree this device tree patch should go
> in through.
>
> > > > +                                             ethernet = <&enetc_port2>;
> > > > +
> > > > +                                             fixed-link {
> > > > +                                                     speed = <2500>;
> > > > +                                                     full-duplex;
> > > > +                                             };
> > >
> > > gmii and 2500 also don't really go together.
> >
> > Not even if you raise the clock frequency?
> >
> > >
> > >      Andrew
> >
> > Thanks,
> > -Vladimir

Correct me if I'm wrong, but I think that PHY_INTERFACE_MODE_INTERNAL
is added by Florian in 2017 as a generalization of the BCM7445 DSA
switch bindings with internal PHY ports, and later became "popular"
with other DSA drivers (ar9331, lantiq gswip). Of those, ar9331 is
actually using phy-mode = "gmii" for the CPU port, and phy-mode =
"internal" for the embedded copper PHYs.
I hate to be making this sort of non-binary decision. Is it a GMII
interface _or_ an internal interface? Prior to 2017, this would have
probably been a non-question. The patch series which adds it does not
clarify "you should use this mode in situation A, and this mode in
situation B" either.

Regards,
-Vladimir

[PATCH devicetree 4/4] arm64: dts: fsl: ls1028a: enable switch PHYs on RDB

[Vladimir Oltean]

From: Claudiu Manoil <claudiu.manoil@nxp.com>

Link the switch PHY nodes to the central MDIO controller PCIe endpoint
node on LS1028A (implemented as PF3) so that PHYs are accessible via
MDIO.

Enable SGMII AN on the Felix PCS by telling PHYLINK that the VSC8514
quad PHY is capable of in-band-status.

The PHYs are used in poll mode due to an issue with the interrupt line
on current revisions of the LS1028A-RDB board.

Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 .../boot/dts/freescale/fsl-ls1028a-rdb.dts    | 51 +++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index afb55653850d..9353c00e46a7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -194,6 +194,57 @@
 	status = "disabled";
 };
 
+&enetc_mdio_pf3 {
+	/* VSC8514 QSGMII quad PHY */
+	qsgmii_phy0: ethernet-phy@10 {
+		reg = <0x10>;
+	};
+
+	qsgmii_phy1: ethernet-phy@11 {
+		reg = <0x11>;
+	};
+
+	qsgmii_phy2: ethernet-phy@12 {
+		reg = <0x12>;
+	};
+
+	qsgmii_phy3: ethernet-phy@13 {
+		reg = <0x13>;
+	};
+};
+
+&mscc_felix_port0 {
+	status = "okay";
+	label = "swp0";
+	managed = "in-band-status";
+	phy-handle = <&qsgmii_phy0>;
+	phy-mode = "qsgmii";
+};
+
+&mscc_felix_port1 {
+	status = "okay";
+	label = "swp1";
+	managed = "in-band-status";
+	phy-handle = <&qsgmii_phy1>;
+	phy-mode = "qsgmii";
+};
+
+&mscc_felix_port2 {
+	status = "okay";
+	label = "swp2";
+	managed = "in-band-status";
+	phy-handle = <&qsgmii_phy2>;
+	phy-mode = "qsgmii";
+};
+
+&mscc_felix_port3 {
+	status = "okay";
+	label = "swp3";
+	managed = "in-band-status";
+	phy-handle = <&qsgmii_phy3>;
+	phy-mode = "qsgmii";
+};
+
 &sai4 {
 	status = "okay";
 };
-- 
2.17.1

Re: [PATCH devicetree 4/4] arm64: dts: fsl: ls1028a: enable switch PHYs on RDB

[Andrew Lunn]

On Mon, Feb 17, 2020 at 04:44:14PM +0200, Vladimir Oltean wrote:
> From: Claudiu Manoil <claudiu.manoil@nxp.com>
> 
> Link the switch PHY nodes to the central MDIO controller PCIe endpoint
> node on LS1028A (implemented as PF3) so that PHYs are accessible via
> MDIO.
> 
> Enable SGMII AN on the Felix PCS by telling PHYLINK that the VSC8514
> quad PHY is capable of in-band-status.
> 
> The PHYs are used in poll mode due to an issue with the interrupt line
> on current revisions of the LS1028A-RDB board.
> 
> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
> Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew