devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Tony Lindgren <tony@atomide.com>
To: linux-omap@vger.kernel.org
Cc: "Benoît Cousson" <bcousson@baylibre.com>,
	devicetree@vger.kernel.org, "Jyri Sarha" <jsarha@ti.com>,
	"Laurent Pinchart" <laurent.pinchart@ideasonboard.com>,
	"Tomi Valkeinen" <tomi.valkeinen@ti.com>,
	Keerthy <j-keerthy@ti.com>, "Sebastian Reichel" <sre@kernel.org>
Subject: [PATCH 09/23] ARM: dts: Configure interconnect target module for omap5 dss
Date: Mon, 24 Feb 2020 13:09:45 -0800	[thread overview]
Message-ID: <20200224210959.56146-10-tony@atomide.com> (raw)
In-Reply-To: <20200224210959.56146-1-tony@atomide.com>

We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" peroperty until the child
devices are probing with ti-sysc interconnect driver.

Initially let's just update the top level dss node to probe with ti-sysc
interconnect target module driver. The child nodes are still children
of dispc, only the node indentation changes for them now along with
using the reg range provided by top level dss.

Cc: Jyri Sarha <jsarha@ti.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/boot/dts/omap5.dtsi | 148 +++++++++++++++++++----------------
 1 file changed, 82 insertions(+), 66 deletions(-)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -292,78 +292,94 @@ target-module@56000000 {
 			 */
 		};
 
-		dss: dss@58000000 {
-			compatible = "ti,omap5-dss";
-			reg = <0x58000000 0x80>;
-			status = "disabled";
+		target-module@58000000 {
+			compatible = "ti,sysc-omap2", "ti,sysc";
 			ti,hwmods = "dss_core";
-			clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
-			clock-names = "fck";
+			reg = <0x58000000 4>,
+			      <0x58000014 4>;
+			reg-names = "rev", "syss";
+			ti,syss-mask = <1>;
+			clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
+				 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
+				 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
+				 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
+			clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges;
+			ranges = <0 0x58000000 0x1000000>;
 
-			dispc@58001000 {
-				compatible = "ti,omap5-dispc";
-				reg = <0x58001000 0x1000>;
-				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-				ti,hwmods = "dss_dispc";
+			dss: dss@0 {
+				compatible = "ti,omap5-dss";
+				reg = <0 0x80>;
+				status = "disabled";
 				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
 				clock-names = "fck";
-			};
-
-			rfbi: encoder@58002000  {
-				compatible = "ti,omap5-rfbi";
-				reg = <0x58002000 0x100>;
-				status = "disabled";
-				ti,hwmods = "dss_rfbi";
-				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
-				clock-names = "fck", "ick";
-			};
-
-			dsi1: encoder@58004000 {
-				compatible = "ti,omap5-dsi";
-				reg = <0x58004000 0x200>,
-				      <0x58004200 0x40>,
-				      <0x58004300 0x40>;
-				reg-names = "proto", "phy", "pll";
-				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-				status = "disabled";
-				ti,hwmods = "dss_dsi1";
-				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
-					 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
-				clock-names = "fck", "sys_clk";
-			};
-
-			dsi2: encoder@58005000 {
-				compatible = "ti,omap5-dsi";
-				reg = <0x58009000 0x200>,
-				      <0x58009200 0x40>,
-				      <0x58009300 0x40>;
-				reg-names = "proto", "phy", "pll";
-				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-				status = "disabled";
-				ti,hwmods = "dss_dsi2";
-				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
-					 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
-				clock-names = "fck", "sys_clk";
-			};
-
-			hdmi: encoder@58060000 {
-				compatible = "ti,omap5-hdmi";
-				reg = <0x58040000 0x200>,
-				      <0x58040200 0x80>,
-				      <0x58040300 0x80>,
-				      <0x58060000 0x19000>;
-				reg-names = "wp", "pll", "phy", "core";
-				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-				status = "disabled";
-				ti,hwmods = "dss_hdmi";
-				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
-					 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
-				clock-names = "fck", "sys_clk";
-				dmas = <&sdma 76>;
-				dma-names = "audio_tx";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0 0x1000000>;
+
+				dispc@1000 {
+					compatible = "ti,omap5-dispc";
+					reg = <0x1000 0x1000>;
+					interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+					ti,hwmods = "dss_dispc";
+					clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+					clock-names = "fck";
+				};
+
+				rfbi: encoder@2000  {
+					compatible = "ti,omap5-rfbi";
+					reg = <0x2000 0x100>;
+					status = "disabled";
+					ti,hwmods = "dss_rfbi";
+					clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
+					clock-names = "fck", "ick";
+				};
+
+				dsi1: encoder@4000 {
+					compatible = "ti,omap5-dsi";
+					reg = <0x4000 0x200>,
+					      <0x4200 0x40>,
+					      <0x4300 0x40>;
+					reg-names = "proto", "phy", "pll";
+					interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+					status = "disabled";
+					ti,hwmods = "dss_dsi1";
+					clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
+						 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
+					clock-names = "fck", "sys_clk";
+				};
+
+				dsi2: encoder@9000 {
+					compatible = "ti,omap5-dsi";
+					reg = <0x9000 0x200>,
+					      <0x9200 0x40>,
+					      <0x9300 0x40>;
+					reg-names = "proto", "phy", "pll";
+					interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+					status = "disabled";
+					ti,hwmods = "dss_dsi2";
+					clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
+						 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
+					clock-names = "fck", "sys_clk";
+				};
+
+				hdmi: encoder@40000 {
+					compatible = "ti,omap5-hdmi";
+					reg = <0x40000 0x200>,
+					      <0x40200 0x80>,
+					      <0x40300 0x80>,
+					      <0x60000 0x19000>;
+					reg-names = "wp", "pll", "phy", "core";
+					interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+					status = "disabled";
+					ti,hwmods = "dss_hdmi";
+					clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
+						 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
+					clock-names = "fck", "sys_clk";
+					dmas = <&sdma 76>;
+					dma-names = "audio_tx";
+				};
 			};
 		};
 
-- 
2.25.1

  parent reply	other threads:[~2020-02-24 21:10 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-24 21:09 [PATCH 00/23] Drop platform data for omap DSS Tony Lindgren
2020-02-24 21:09 ` [PATCH 01/23] ARM: dts: Configure interconnect target module for omap4 dss Tony Lindgren
2020-02-24 21:09 ` [PATCH 02/23] ARM: dts: Configure interconnect target module for omap4 dispc Tony Lindgren
2020-02-24 21:09 ` [PATCH 03/23] ARM: dts: Configure interconnect target module for omap4 rfbi Tony Lindgren
2020-02-24 21:09 ` [PATCH 04/23] ARM: dts: Configure interconnect target module for omap4 venc Tony Lindgren
2020-02-24 21:09 ` [PATCH 05/23] ARM: dts: Configure interconnect target module for omap4 dsi1 Tony Lindgren
2020-02-24 21:09 ` [PATCH 06/23] ARM: dts: Configure interconnect target module for omap4 dsi2 Tony Lindgren
2020-02-24 21:09 ` [PATCH 07/23] ARM: dts: Configure interconnect target module for omap4 hdmi Tony Lindgren
2020-02-24 21:09 ` [PATCH 08/23] ARM: OMAP2+: Drop legacy platform data for omap4 dss Tony Lindgren
2020-02-24 21:09 ` Tony Lindgren [this message]
2020-02-24 21:09 ` [PATCH 10/23] ARM: dts: Configure interconnect target module for omap5 dispc Tony Lindgren
2020-02-24 21:09 ` [PATCH 11/23] ARM: dts: Configure interconnect target module for omap5 rfbi Tony Lindgren
2020-02-24 21:09 ` [PATCH 12/23] ARM: dts: Configure interconnect target module for omap5 dsi1 Tony Lindgren
2020-02-24 21:09 ` [PATCH 13/23] ARM: dts: Configure interconnect target module for omap5 dsi2 Tony Lindgren
2020-02-24 21:09 ` [PATCH 14/23] ARM: dts: Configure interconnect target module for omap5 hdmi Tony Lindgren
2020-02-24 21:09 ` [PATCH 15/23] ARM: OMAP2+: Drop legacy platform data for omap5 DSS Tony Lindgren
2020-02-24 21:09 ` [PATCH 16/23] ARM: dts: Configure interconnect target module for dra7 dss Tony Lindgren
2020-02-24 21:09 ` [PATCH 17/23] ARM: dts: Configure interconnect target module for dra7 dispc Tony Lindgren
2020-02-24 21:09 ` [PATCH 18/23] ARM: dts: Configure interconnect target module for dra7 hdmi Tony Lindgren
2020-02-24 21:09 ` [PATCH 19/23] ARM: OMAP2+: Drop legacy platform data for dra7 DSS Tony Lindgren
2020-02-24 21:09 ` [PATCH 20/23] ARM: dts: Move am437x dss to the interconnect target module in l4 Tony Lindgren
2020-02-24 21:09 ` [PATCH 21/23] ARM: dts: Configure interconnect target module for am437x dispc Tony Lindgren
2020-02-24 21:09 ` [PATCH 22/23] ARM: dts: Configure interconnect target module for am437x rfbi Tony Lindgren
2020-02-24 21:09 ` [PATCH 23/23] ARM: OMAP2+: Drop legacy platform data for am437x DSS Tony Lindgren
2020-02-24 21:21 ` [PATCH 00/23] Drop platform data for omap DSS Laurent Pinchart
2020-02-24 21:30   ` Tony Lindgren

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200224210959.56146-10-tony@atomide.com \
    --to=tony@atomide.com \
    --cc=bcousson@baylibre.com \
    --cc=devicetree@vger.kernel.org \
    --cc=j-keerthy@ti.com \
    --cc=jsarha@ti.com \
    --cc=laurent.pinchart@ideasonboard.com \
    --cc=linux-omap@vger.kernel.org \
    --cc=sre@kernel.org \
    --cc=tomi.valkeinen@ti.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).