From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3F0EC10F26 for ; Fri, 6 Mar 2020 14:43:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BEB0D208CD for ; Fri, 6 Mar 2020 14:43:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727578AbgCFOnq (ORCPT ); Fri, 6 Mar 2020 09:43:46 -0500 Received: from foss.arm.com ([217.140.110.172]:34844 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727059AbgCFOno (ORCPT ); Fri, 6 Mar 2020 09:43:44 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5F34831B; Fri, 6 Mar 2020 06:43:43 -0800 (PST) Received: from arm.com (e112269-lin.cambridge.arm.com [10.1.195.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 132703F534; Fri, 6 Mar 2020 06:43:40 -0800 (PST) Date: Fri, 6 Mar 2020 14:43:36 +0000 From: Steven Price To: Rob Herring Cc: Nick Fan , Nicolas Boichat , Sj Huang , David Airlie , Daniel Vetter , Mark Rutland , Matthias Brugger , Tomeu Vizoso , Alyssa Rosenzweig , Liam Girdwood , Mark Brown , dri-devel , Devicetree List , lkml , linux-arm Mailing List , "moderated list:ARM/Mediatek SoC support" , Hsin-Yi Wang , Ulf Hansson Subject: Re: [PATCH v4 1/7] dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183 Message-ID: <20200306144336.GA9234@arm.com> References: <20200207052627.130118-1-drinkcat@chromium.org> <20200207052627.130118-2-drinkcat@chromium.org> <20200225171613.GA7063@bogus> <1583462055.4947.6.camel@mtksdaap41> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Mar 06, 2020 at 02:13:08PM +0000, Rob Herring wrote: > On Thu, Mar 5, 2020 at 8:34 PM Nick Fan wrote: > > > > Sorry for my late reply. > > I have checked internally. > > The MT8183_POWER_DOMAIN_MFG_2D is just a legacy name, not really 2D > > domain. > > > > If the naming too confusing, we can change this name to > > MT8183_POWER_DOMAIN_MFG_CORE2 for consistency. > > Can you clarify what's in each domain? Are there actually 3 shader > cores (IIRC, that should be discoverable)? The cover letter from Nicolas includes: > [ 501.321752] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1 0x7 is three bits set, so it certainly looks like there are 3 shader cores. Of course I wouldn't guarantee that it is as simple as each power domain has a shader core in. The job manager and tiler also need to be powered somehow, so they are either sharing with a shader core or there's something more complex going on. Steve