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[217.229.22.169]) by smtp.gmail.com with ESMTPSA id t18sm5049212wml.17.2020.03.10.10.13.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 10:13:39 -0700 (PDT) Date: Tue, 10 Mar 2020 18:13:38 +0100 From: Thierry Reding To: Dmitry Osipenko Cc: Jon Hunter , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd , Joseph Lo , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v5 5/8] memory: tegra: Add EMC scaling support code for Tegra210 Message-ID: <20200310171338.GF3079591@ulmo> References: <20200310152003.2945170-1-thierry.reding@gmail.com> <20200310152003.2945170-6-thierry.reding@gmail.com> <4ea3a96f-52cb-4eab-cf92-932f6882ad85@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="NGIwU0kFl1Z1A3An" Content-Disposition: inline In-Reply-To: <4ea3a96f-52cb-4eab-cf92-932f6882ad85@gmail.com> User-Agent: Mutt/1.13.1 (2019-12-14) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org --NGIwU0kFl1Z1A3An Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Mar 10, 2020 at 07:43:12PM +0300, Dmitry Osipenko wrote: > 10.03.2020 18:20, Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > From: Joseph Lo > >=20 > > This is the initial patch for Tegra210 EMC frequency scaling. It has the > > code to program various aspects of the EMC that are standardized, but it > > does not yet include the specific programming sequence needed for clock > > scaling. > >=20 > > The driver is designed to support LPDDR4 SDRAM. Devices that use LPDDR4 > > need to perform training of the RAM before it can be used. Firmware will > > perform this training during early boot and pass a table of supported > > frequencies to the kernel via device tree. > >=20 > > For the frequencies above 800 MHz, periodic retraining is needed to > > compensate for changes in timing. This periodic training will have to be > > performed until the frequency drops back to or below 800 MHz. > >=20 > > This driver provides helpers used during this runtime retraining that > > will be used by the sequence specific code in a follow-up patch. > >=20 > > Based on work by Peter De Schrijver . > >=20 > > Signed-off-by: Joseph Lo > > Signed-off-by: Thierry Reding > > --- > > Changes in v5: > > - major rework and cleanup > >=20 > > drivers/memory/tegra/tegra210-emc.c | 1952 +++++++++++++++++++++------ > > drivers/memory/tegra/tegra210-emc.h | 893 +++++++++++- > > 2 files changed, 2390 insertions(+), 455 deletions(-) > >=20 > > diff --git a/drivers/memory/tegra/tegra210-emc.c b/drivers/memory/tegra= /tegra210-emc.c > > index 80ea14d1e6ce..4ea8fb70a4fd 100644 > > --- a/drivers/memory/tegra/tegra210-emc.c > > +++ b/drivers/memory/tegra/tegra210-emc.c > > @@ -1,6 +1,6 @@ > > // SPDX-License-Identifier: GPL-2.0 > > /* > > - * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved. > > + * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. > > */ >=20 > Would be nice to avoid all the unnecessary changes, like the one above > and then all the code's removals/reshuffling. >=20 > Such that a new patch was a clean addition to a previous patch, instead > of a re-write. I think this is the result of me messing up a rebase. The EMC driver changes added in the clock driver patch should've been in this patch, which would've made this a clean addition. I'll reshuffle the code for the next revision. Thanks for pointing that out. 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