From: Rob Herring <robh@kernel.org>
To: Dhananjay Kangude <dkangude@cadence.com>
Cc: linux-edac@vger.kernel.org, bp@alien8.de, mchehab@kernel.org,
tony.luck@intel.com, james.morse@arm.com,
linux-kernel@vger.kernel.org, mparab@cadence.com,
devicetree@vger.kernel.org
Subject: Re: [PATCH v1 2/2] dt-bindings: edac: Add cadence ddr mc support
Date: Tue, 10 Mar 2020 13:44:47 -0500 [thread overview]
Message-ID: <20200310184447.GB2508@bogus> (raw)
In-Reply-To: <20200228094322.13617-3-dkangude@cadence.com>
On Fri, Feb 28, 2020 at 10:43:22AM +0100, Dhananjay Kangude wrote:
> Add documentation for cadence ddr memory controller EDAC DTS bindings
>
> Signed-off-by: Dhananjay Kangude <dkangude@cadence.com>
> ---
> .../devicetree/bindings/edac/cdns,ddr-edac.yaml | 59 ++++++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml
>
> diff --git a/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml
> new file mode 100644
> index 000000000000..d83d8840d57b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/edac/cdns,ddr-edac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cadence DDR IP with ECC support (EDAC)
> +
> +description:
> + This binding describes the Cadence DDR/LPDDR IP with ECC feature enabled
> + to detect and correct CE/UE errors.
> +
> +maintainers:
> + - Dhananjay Kangdue <dkangude@cadence.com>
> +
> +properties:
> + compatible:
> + enum:
> + - cdns,cadence-ddr4-mc-edac
You have Cadence twice effectively.
'edac' is a linuxism. The binding should be for the DDR controller
unless this block only does ECC. Name it based on what the h/w is
called.
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 1
> +
> + ranges: true
You don't have any children defined, so you don't need these 3
properties.
> +
> + reg:
> + minItems: 1
> + maxItems: 2
> + items:
> + - description:
> + Register block of DDR/LPDDR apb registers up to mapped area.
> + Mapped area contains the register set for memory controller,
> + phy and PI module register set doesn't part of this mapping.
> +
> + interrupts:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - ranges
> + - reg
> + - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + edac: edac@fd100000 {
> + compatible = "cdns,cadence-ddr4-mc-edac";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + reg = <0xfd100000 0x4000>;
> + interrupts = <0x00 0x01 0x04>;
> + };
Wrong indent.
> +...
> --
> 2.15.0
>
prev parent reply other threads:[~2020-03-10 18:44 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-28 9:43 [PATCH v1 0/2] Add EDAC support for Cadence ddr controller Dhananjay Kangude
2020-02-28 9:43 ` [PATCH v1 1/2] EDAC/Cadence:Add EDAC driver for cadence memory controller Dhananjay Kangude
2020-03-20 17:41 ` Borislav Petkov
2020-02-28 9:43 ` [PATCH v1 2/2] dt-bindings: edac: Add cadence ddr mc support Dhananjay Kangude
2020-03-10 18:44 ` Rob Herring [this message]
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