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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id 67sm6993332oid.30.2020.03.12.14.25.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 14:25:58 -0700 (PDT) Received: (nullmailer pid 27240 invoked by uid 1000); Thu, 12 Mar 2020 21:25:57 -0000 Date: Thu, 12 Mar 2020 16:25:57 -0500 From: Rob Herring To: Arnd Bergmann List-Id: Cc: Sergey.Semin@baikalelectronics.ru, Serge Semin , Alexey Malahov , Maxim Kaurkin , Pavel Parkhomenko , Ramil Zaripov , Ekaterina Skachko , Vadim Vlasov , Thomas Bogendoerfer , Paul Burton , Ralf Baechle , Mark Rutland , Olof Johansson , SoC Team , DTML , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 0/6] soc: Add Baikal-T1 SoC APB/AXI EHB and L2-cache drivers Message-ID: <20200312212557.GB27332@bogus> References: <20200306130731.938808030702@mail.baikalelectronics.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Mar 06, 2020 at 04:19:47PM +0100, Arnd Bergmann wrote: > On Fri, Mar 6, 2020 at 2:07 PM wrote: > > > > From: Serge Semin > > > > Aside from PCIe/SATA/DDR/I2C/CPU-reboot specific settings the Baikal-T1 > > system controller provides three vendor-specific blocks. In particular > > there are two Errors Handler Blocks to detect and report an info regarding > > any problems discovered on the AXI and APB buses. These are the main buses > > utilized by the SoC devices to interact with each other. In addition there > > is a way to tune the MIPS P5600 CM2 L2-cache up by setting the Tag/Data/WS > > L2-to-RAM latencies. All of this functionality is implemented in the > > APB/AXI EHB and L2-cache control block drivers to be a part of the kernel soc > > subsystem (as being specific to the Baikal-T1 SoC) and introduced in the > > framework of this patchset. > > > > This patchset is rebased and tested on the mainline Linux kernel 5.6-rc4: > > commit 98d54f81e36b ("Linux 5.6-rc4"). > > I have no objection to the drivers, but I wonder if these should be > in drivers/bus and drivers/memory instead of drivers/soc, which have > similar drivers already. The driver for the L2 cache is not really a > memory controller driver, but it may be close enough, and we > already have a couple of different things in there. I don't have the driver side in my inbox, but isn't setting up cache latencies in a driver a little late? Rob