From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 326B1C4332E for ; Fri, 20 Mar 2020 09:45:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 11A1E20722 for ; Fri, 20 Mar 2020 09:45:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726690AbgCTJpp (ORCPT ); Fri, 20 Mar 2020 05:45:45 -0400 Received: from lucky1.263xmail.com ([211.157.147.135]:37492 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726527AbgCTJpp (ORCPT ); Fri, 20 Mar 2020 05:45:45 -0400 Received: from localhost (unknown [192.168.167.32]) by lucky1.263xmail.com (Postfix) with ESMTP id B1A4E6A714; Fri, 20 Mar 2020 17:34:02 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from ubuntu18.lan (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P19134T140660085376768S1584696835111908_; Fri, 20 Mar 2020 17:34:03 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <4a96f71f51da89c82dca12d4b69f0e0f> X-RL-SENDER: yifeng.zhao@rock-chips.com X-SENDER: zyf@rock-chips.com X-LOGIN-NAME: yifeng.zhao@rock-chips.com X-FST-TO: miquel.raynal@bootlin.com X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Yifeng Zhao To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-mtd@lists.infradead.org, heiko@sntech.de, linux-rockchip@lists.infradead.org, Yifeng Zhao Subject: [PATCH v4 2/3] dt-bindings: mtd: Describe Rockchip RK3xxx NAND flash controller Date: Fri, 20 Mar 2020 17:33:41 +0800 Message-Id: <20200320093342.15470-3-yifeng.zhao@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200320093342.15470-1-yifeng.zhao@rock-chips.com> References: <20200320093342.15470-1-yifeng.zhao@rock-chips.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Documentation support for Rockchip RK3xxx NAND flash controllers Signed-off-by: Yifeng Zhao --- Changes in v4: - The compatible define with rkxx_nfc - Add assigned-clocks - Fix some wrong define Changes in v3: - Change the title for the dt-bindings Changes in v2: None .../bindings/mtd/rockchip,nand.yaml | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/rockchip,nand.yaml diff --git a/Documentation/devicetree/bindings/mtd/rockchip,nand.yaml b/Documentation/devicetree/bindings/mtd/rockchip,nand.yaml new file mode 100644 index 000000000000..907af0d52b6b --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/rockchip,nand.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/rockchip,nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoCs NAND FLASH Controller (NFC) Device Tree Bindings + +allOf: + - $ref: "nand-controller.yaml" + +maintainers: + - Yifeng Zhao + +properties: + "#address-cells": true + "#size-cells": true + + compatible: + enum: + - rockchip,px30_nfc + - rockchip,rk3308_nfc + - rockchip,rv1108_nfc + - rockchip,rk3066_nfc + - rockchip,rk3188_nfc + - rockchip,rk3288_nfc + - rockchip,rk3368_nfc + - rockchip,rk2928_nfc + - rockchip,rk3036_nfc + - rockchip,rk3128_nfc + - rockchip,rk3228_nfc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Module Clock + - description: Bus Clock + + clock-names: + items: + - const: nfc + - const: ahb + +patternProperties: + "^nand@[0-3]$": + type: object + properties: + reg: + minimum: 0 + maximum: 3 + + nand-ecc-step-size: + const: 1024 + + nand-ecc-strength: + enum: [16, 24 , 40, 60, 70] + + nand-bus-width: + const: 8 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + #include + #include + nfc: nand-controller@ff4b0000 { + compatible = "rockchip,nfc"; + reg = <0x0 0xff4b0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; + clock-names = "nfc", "ahb"; + assigned-clocks = <&clks SCLK_NANDC>; + assigned-clock-rates = <150000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&flash_csn0 &flash_rdy &flash_ale &flash_cle + &flash_wrn &flash_rdn &flash_bus8>; + + #address-cells = <1>; + #size-cells = <0>; + nand@0 { + reg = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + nand-bus-width = <8>; + }; + }; + +... -- 2.17.1