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From: Philipp Zabel <p.zabel@pengutronix.de>
To: linux-media@vger.kernel.org
Cc: Ezequiel Garcia <ezequiel@collabora.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Hans Verkuil <hverkuil@xs4all.nl>,
	Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
	kernel@pengutronix.de, devicetree@vger.kernel.org
Subject: [PATCH v6 3/4] arm64: dts: imx8mq: enable Hantro G1/G2 VPU
Date: Fri, 20 Mar 2020 14:12:55 +0100	[thread overview]
Message-ID: <20200320131256.23294-4-p.zabel@pengutronix.de> (raw)
In-Reply-To: <20200320131256.23294-1-p.zabel@pengutronix.de>

Add the i.MX8MQ VPU module which comprises Hantro G1 and G2 video
decoder cores and a reset/control block.

Hook up the bus clock to the VPU power domain to enable handshakes, and
configure the core clocks to 600 MHz and the bus clock to 800 MHz by
default.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
New in v6.
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 27 +++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 6a1e83922c71..98e464ecb68a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -666,6 +666,7 @@
 					pgc_vpu: power-domain@6 {
 						#power-domain-cells = <0>;
 						reg = <IMX8M_POWER_DOMAIN_VPU>;
+						clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
 					};
 
 					pgc_disp: power-domain@7 {
@@ -1130,6 +1131,32 @@
 			status = "disabled";
 		};
 
+		vpu: video-codec@38300000 {
+			compatible = "nxp,imx8mq-vpu";
+			reg = <0x38300000 0x10000>,
+			      <0x38310000 0x10000>,
+			      <0x38320000 0x10000>;
+			reg-names = "g1", "g2", "ctrl";
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "g1", "g2";
+			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+				 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+			clock-names = "g1", "g2", "bus";
+			assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
+					  <&clk IMX8MQ_CLK_VPU_G2>,
+					  <&clk IMX8MQ_CLK_VPU_BUS>,
+					  <&clk IMX8MQ_VPU_PLL_BYPASS>;
+			assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
+						 <&clk IMX8MQ_VPU_PLL_OUT>,
+						 <&clk IMX8MQ_SYS1_PLL_800M>,
+						 <&clk IMX8MQ_VPU_PLL>;
+			assigned-clock-rates = <600000000>, <600000000>,
+					       <800000000>, <0>;
+			power-domains = <&pgc_vpu>;
+		};
+
 		pcie0: pcie@33800000 {
 			compatible = "fsl,imx8mq-pcie";
 			reg = <0x33800000 0x400000>,
-- 
2.20.1


  parent reply	other threads:[~2020-03-20 13:13 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-20 13:12 [PATCH v6 0/4] Add initial i.MX8MQ support Philipp Zabel
2020-03-20 13:12 ` [PATCH v6 1/4] media: dt-bindings: Document i.MX8MQ VPU bindings Philipp Zabel
2020-03-20 17:25   ` Rob Herring
2020-03-20 13:12 ` [PATCH v6 2/4] media: hantro: add initial i.MX8MQ support Philipp Zabel
2020-03-20 13:12 ` Philipp Zabel [this message]
2020-05-27 16:19   ` [PATCH v6 3/4] arm64: dts: imx8mq: enable Hantro G1/G2 VPU Philipp Zabel
2020-05-28  1:02     ` Ezequiel Garcia
2020-06-10  0:19       ` Ezequiel Garcia
2020-06-16 14:07   ` Shawn Guo
2020-03-20 13:12 ` [PATCH v6 4/4] media: MAINTAINERS: add myself to co-maintain Hantro G1/G2 for i.MX8MQ Philipp Zabel
2020-03-23 22:41 ` [PATCH v6 0/4] Add initial i.MX8MQ support Ezequiel Garcia

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