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[217.229.28.220]) by smtp.gmail.com with ESMTPSA id c85sm8259057wmd.48.2020.03.20.08.04.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Mar 2020 08:04:07 -0700 (PDT) Date: Fri, 20 Mar 2020 16:04:06 +0100 From: Thierry Reding To: Dmitry Osipenko Cc: Thomas Gleixner , Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/7] clocksource: Add Tegra186 timers support Message-ID: <20200320150406.GA3706404@ulmo> References: <20200320133452.3705040-1-thierry.reding@gmail.com> <20200320133452.3705040-3-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="OXfL5xGRrasGEqWY" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.13.1 (2019-12-14) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org --OXfL5xGRrasGEqWY Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Mar 20, 2020 at 05:39:01PM +0300, Dmitry Osipenko wrote: > 20.03.2020 16:34, Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > From: Thierry Reding > >=20 > > Currently this only supports a single watchdog, which uses a timer in > > the background for countdown. Eventually the timers could be used for > > various time-keeping tasks, but by default the architected timer will > > already provide that functionality. > >=20 > > Signed-off-by: Thierry Reding > > --- > > drivers/clocksource/Kconfig | 8 + > > drivers/clocksource/Makefile | 1 + > > drivers/clocksource/timer-tegra186.c | 377 +++++++++++++++++++++++++++ > > 3 files changed, 386 insertions(+) > > create mode 100644 drivers/clocksource/timer-tegra186.c > Hello Thierry, >=20 > Shouldn't this driver reside in drivers/watchdog/? Like it's done in a > case of the T30+ driver. The hardware block that this binds to is primarily a time-keeping block that just so happens to also implement a watchdog. Moving this to drivers/watchdog would put us into an odd situation if we ever added code to also implement the time-keeping bits for this hardware. I also think that the way this is done on Tegra30 was a bad choice. The problem is that we now have two drivers (tegra_wdt.c and tegra-timer.c) that both access the same region of memory. This seems to be relatively safe to do on those chips because there's no overlap between the timer and the watchdog interfaces, but on Tegra186 and later the watchdog is actually using one of the timers, so we'd have to be extra careful how to coordinate between the two. It seems much easier to do that by having everything in the same driver and have that register multiple devices in the system. > > +static int __maybe_unused tegra186_timer_suspend(struct device *dev) > > +{ > > + return 0; > > +} > > + > > +static int __maybe_unused tegra186_timer_resume(struct device *dev) > > +{ > > + return 0; > > +} > > + > > +static SIMPLE_DEV_PM_OPS(tegra186_timer_pm_ops, tegra186_timer_suspend, > > + tegra186_timer_resume); >=20 > Perhaps will be better to remove these OPS for now? Yeah, I suppose I could remove those. Although... perhaps I should just try and make this work properly. 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