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[77.57.203.148]) by smtp.gmail.com with ESMTPSA id x1sm9392665wmj.24.2020.03.29.02.21.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Mar 2020 02:21:13 -0700 (PDT) Date: Sun, 29 Mar 2020 11:20:33 +0200 From: Stefan Eichenberger To: Rabeeh Khoury Cc: Baruch Siach , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Russell King Subject: Re: [PATCH] arm64: dts: clearfog-gt-8k: fix ge phy reset pin Message-ID: <20200329092032.GA4620@eichest-laptop> References: <20200328212115.12477-1-eichest@gmail.com> <877dz3el4k.fsf@tarshish> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Rabeeh and Baruch On Sun, Mar 29, 2020 at 11:42:35AM +0300, Rabeeh Khoury wrote: > On Sun, Mar 29, 2020 at 9:22 AM Baruch Siach wrote: > > > > Hi Stefan, > > > > On Sun, Mar 29 2020, eichest@gmail.com wrote: > > > From: Stefan Eichenberger > > > > > > According to the ClearFog-GT-8K-rev-1_1-Simplified-Schematic the reset > > > pin for the gigabit phy is MPP62 and not MPP43. > > > > Have you tested that on real hardware? > > > > The 1Gb PHY reset on my Clearfog GT-8K is connected to MPP43. Russell's > > commit 46f94c7818e7 ("arm64: dts: clearfog-gt-8k: set gigabit PHY reset > > deassert delay") indicates that this is the case on his board as well. > > > > In case there was a hardware change between board revisions, we need > > another dtb for that revision. > > It's a bug in the simplified schematics since that schematics is based > on rev 1.0 and not rev 1.1 as claimed. > > In rev 1.0; the 1Gbps phy reset was connected to MPP62; but that MPP > is not functional as a GPIO when selecting MPP[56:61] as SD card. > Due to that we manually rewired ALL rev 1.0 PCBs 1Gbps phy to be > connected to MPP43 via R8038 pads. > > Rev 1.1 fixes this by that by disconnecting 1Gbps phy reset from MPP62 > and wiring it to MPP43. > So basically rev 1.0 and rev 1.1 are compatible software wise. We will > fix the schematics. Ahh now I see, I didn't enable the phy driver when I did the test with the default devicetree and then when I changed the devicetree I also enabled the driver, that's my fault. Sorry for the confusion... I can confirm that it works with MPP43. Thanks for the clarification! Regards, Stefan