From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31327C43331 for ; Tue, 31 Mar 2020 08:32:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 04E9620787 for ; Tue, 31 Mar 2020 08:32:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=st.com header.i=@st.com header.b="yAvTZNfI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729819AbgCaIcW (ORCPT ); Tue, 31 Mar 2020 04:32:22 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:5554 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726528AbgCaIcW (ORCPT ); Tue, 31 Mar 2020 04:32:22 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 02V8RAxx026921; Tue, 31 Mar 2020 10:32:05 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=X8iisE1igCwvJ2PS0MtddghezBylam8p0N46lMHrHxg=; b=yAvTZNfIB37X4zenAhDyktg5PBGgHRcnPc9yhbeGBbjjRe++S5jNn40tmYrEp/17Nfx/ DzUSA6nnyoCgk/MDdH2pIMvZZsk4XcCDRxDcI5iP0O2ZQUqhtyHREUcVXGac/ZyUuIGB HJ6Kl7wVNA8ExR25uqlsHs24MzG+8zdOGSEYAiXMzZxwC84Jk0xR3gbIEV8KpY8rgpnZ rpptgQfzGXYYERzO5kknDUZ1iKcUcLLRjRvgj+EOVbeEIuVrnvnPD8sM/2iNljRHy8gP 0OgYzmkwDwnXxAHuFU/YMJDrDVoeJICdtE675bf1dYC7uaGLucTlGkezQFvdUAP+AaQF dQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 301vkdp6ra-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 31 Mar 2020 10:32:05 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 38D5510003B; Tue, 31 Mar 2020 10:32:04 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag3node3.st.com [10.75.127.9]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2227221E677; Tue, 31 Mar 2020 10:32:04 +0200 (CEST) Received: from localhost (10.75.127.45) by SFHDAG3NODE3.st.com (10.75.127.9) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 31 Mar 2020 10:32:03 +0200 From: Benjamin Gaignard To: , , , , , , , CC: , , , , Benjamin Gaignard Subject: [PATCH v5 3/6] mfd: stm32: Add defines to be used for clkevent purpose Date: Tue, 31 Mar 2020 10:31:43 +0200 Message-ID: <20200331083146.10462-4-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20200331083146.10462-1-benjamin.gaignard@st.com> References: <20200331083146.10462-1-benjamin.gaignard@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG1NODE3.st.com (10.75.127.3) To SFHDAG3NODE3.st.com (10.75.127.9) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.676 definitions=2020-03-31_03:2020-03-30,2020-03-31 signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add defines to be able to enable/clear irq and configure one shot mode. Signed-off-by: Benjamin Gaignard Acked-by: Lee Jones --- version 5: - no change version 4: - move defines in mfd/stm32-lptimer.h include/linux/mfd/stm32-lptimer.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/linux/mfd/stm32-lptimer.h b/include/linux/mfd/stm32-lptimer.h index 605f62264825..90b20550c1c8 100644 --- a/include/linux/mfd/stm32-lptimer.h +++ b/include/linux/mfd/stm32-lptimer.h @@ -27,10 +27,15 @@ #define STM32_LPTIM_CMPOK BIT(3) /* STM32_LPTIM_ICR - bit fields */ +#define STM32_LPTIM_ARRMCF BIT(1) #define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3) +/* STM32_LPTIM_IER - bit flieds */ +#define STM32_LPTIM_ARRMIE BIT(1) + /* STM32_LPTIM_CR - bit fields */ #define STM32_LPTIM_CNTSTRT BIT(2) +#define STM32_LPTIM_SNGSTRT BIT(1) #define STM32_LPTIM_ENABLE BIT(0) /* STM32_LPTIM_CFGR - bit fields */ -- 2.15.0