From: Matthias Kaehlcke <mka@chromium.org>
To: Douglas Anderson <dianders@chromium.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: sc7180: Swap order of gpucc and sdhc_2
Date: Tue, 31 Mar 2020 09:56:20 -0700 [thread overview]
Message-ID: <20200331165620.GF199755@google.com> (raw)
In-Reply-To: <20200331092832.1.Ic361058ca22d7439164ffea11421740462e14272@changeid>
On Tue, Mar 31, 2020 at 09:29:00AM -0700, Douglas Anderson wrote:
> Devices are supposed to be sorted by unit address. These two got
> swapped when they landed. Fix.
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> ---
>
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 998f101ad623..4bdadfd9efb9 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -1294,6 +1294,20 @@ pinconf-sd-cd {
> };
> };
>
> + gpucc: clock-controller@5090000 {
> + compatible = "qcom,sc7180-gpucc";
> + reg = <0 0x05090000 0 0x9000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> + clock-names = "bi_tcxo",
> + "gcc_gpu_gpll0_clk_src",
> + "gcc_gpu_gpll0_div_clk_src";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> sdhc_2: sdhci@8804000 {
> compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
> reg = <0 0x08804000 0 0x1000>;
> @@ -1312,20 +1326,6 @@ sdhc_2: sdhci@8804000 {
> status = "disabled";
> };
>
> - gpucc: clock-controller@5090000 {
> - compatible = "qcom,sc7180-gpucc";
> - reg = <0 0x05090000 0 0x9000>;
> - clocks = <&rpmhcc RPMH_CXO_CLK>,
> - <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> - clock-names = "bi_tcxo",
> - "gcc_gpu_gpll0_clk_src",
> - "gcc_gpu_gpll0_div_clk_src";
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - #power-domain-cells = <1>;
> - };
> -
> qspi: spi@88dc000 {
> compatible = "qcom,qspi-v1";
> reg = <0 0x088dc000 0 0x600>;
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
prev parent reply other threads:[~2020-03-31 16:56 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-31 16:29 [PATCH] arm64: dts: sc7180: Swap order of gpucc and sdhc_2 Douglas Anderson
2020-03-31 16:56 ` Matthias Kaehlcke [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200331165620.GF199755@google.com \
--to=mka@chromium.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=dianders@chromium.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).