From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96EC0C2BA80 for ; Mon, 6 Apr 2020 11:19:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6E9BA206F5 for ; Mon, 6 Apr 2020 11:19:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="SkglU31c" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727354AbgDFLTk (ORCPT ); Mon, 6 Apr 2020 07:19:40 -0400 Received: from perceval.ideasonboard.com ([213.167.242.64]:43732 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726873AbgDFLTk (ORCPT ); Mon, 6 Apr 2020 07:19:40 -0400 Received: from pendragon.ideasonboard.com (81-175-216-236.bb.dnainternet.fi [81.175.216.236]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 3EB6580E; Mon, 6 Apr 2020 13:19:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1586171977; bh=IWAE7fiWWyJbCmxMSYZ4nVedZ7TWLiwjdCOV/Y+r3m8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=SkglU31c+fBP8OWeHF+yPqdtpqZrPAityh1sgKtfRd/Di6FH3FFVquLsmID4/GZhx ZljmH3/uAyY70/GJcPIzifM+FdVU0lagTxBPoq4xJSKlWMCkoeJDOxMEEy8tTT0M5t l2Pic+wrgl/mayMY9hVJPrZnFqg7Y6LlevSBy+uQ= Date: Mon, 6 Apr 2020 14:19:27 +0300 From: Laurent Pinchart To: Maxime Ripard Cc: Laurent Pinchart , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, Rob Herring , Philipp Zabel , Mark Yao , Sandy Huang , Chen-Yu Tsai Subject: Re: [PATCH/RFC 4/6] dt-bindings: display: rockchip: dw-hdmi: Convert binding to YAML Message-ID: <20200406111927.GD4757@pendragon.ideasonboard.com> References: <20200405233935.27599-1-laurent.pinchart+renesas@ideasonboard.com> <20200405233935.27599-5-laurent.pinchart+renesas@ideasonboard.com> <20200406080032.zlszhkjqmjeoa4ti@gilmour.lan> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20200406080032.zlszhkjqmjeoa4ti@gilmour.lan> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Maxime, On Mon, Apr 06, 2020 at 10:00:32AM +0200, Maxime Ripard wrote: > On Mon, Apr 06, 2020 at 02:39:33AM +0300, Laurent Pinchart wrote: > > Convert the Rockchip HDMI TX text binding to YAML. > > > > Signed-off-by: Laurent Pinchart > > --- > > .../display/rockchip/dw_hdmi-rockchip.txt | 74 -------- > > .../display/rockchip/rockchip,dw-hdmi.yaml | 178 ++++++++++++++++++ > > 2 files changed, 178 insertions(+), 74 deletions(-) > > delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt > > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml > > > > diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt > > deleted file mode 100644 > > index 3d32ce137e7f..000000000000 > > --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt > > +++ /dev/null > > @@ -1,74 +0,0 @@ > > -Rockchip DWC HDMI TX Encoder > > -============================ > > - > > -The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP > > -with a companion PHY IP. > > - > > -These DT bindings follow the Synopsys DWC HDMI TX bindings defined in > > -Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the > > -following device-specific properties. > > - > > - > > -Required properties: > > - > > -- compatible: should be one of the following: > > - "rockchip,rk3228-dw-hdmi" > > - "rockchip,rk3288-dw-hdmi" > > - "rockchip,rk3328-dw-hdmi" > > - "rockchip,rk3399-dw-hdmi" > > -- reg: See dw_hdmi.txt. > > -- reg-io-width: See dw_hdmi.txt. Shall be 4. > > -- interrupts: HDMI interrupt number > > -- clocks: See dw_hdmi.txt. > > -- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. > > -- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0 > > - corresponding to the video input of the controller. The port shall have two > > - endpoints, numbered 0 and 1, connected respectively to the vopb and vopl. > > -- rockchip,grf: Shall reference the GRF to mux vopl/vopb. > > - > > -Optional properties > > - > > -- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master > > - or the functionally-reduced I2C master contained in the DWC HDMI. When > > - connected to a system I2C master this property contains a phandle to that > > - I2C master controller. > > -- clock-names: See dw_hdmi.txt. The "cec" clock is optional. > > -- clock-names: May contain "cec" as defined in dw_hdmi.txt. > > -- clock-names: May contain "grf", power for grf io. > > -- clock-names: May contain "vpll", external clock for some hdmi phy. > > -- phys: from general PHY binding: the phandle for the PHY device. > > -- phy-names: Should be "hdmi" if phys references an external phy. > > - > > -Optional pinctrl entry: > > -- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi > > - will switch to the unwedge pinctrl state for 10ms if it ever gets an > > - i2c timeout. It's intended that this unwedge pinctrl entry will > > - cause the SDA line to be driven low to work around a hardware > > - errata. > > - > > -Example: > > - > > -hdmi: hdmi@ff980000 { > > - compatible = "rockchip,rk3288-dw-hdmi"; > > - reg = <0xff980000 0x20000>; > > - reg-io-width = <4>; > > - ddc-i2c-bus = <&i2c5>; > > - rockchip,grf = <&grf>; > > - interrupts = ; > > - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; > > - clock-names = "iahb", "isfr"; > > - ports { > > - hdmi_in: port { > > - #address-cells = <1>; > > - #size-cells = <0>; > > - hdmi_in_vopb: endpoint@0 { > > - reg = <0>; > > - remote-endpoint = <&vopb_out_hdmi>; > > - }; > > - hdmi_in_vopl: endpoint@1 { > > - reg = <1>; > > - remote-endpoint = <&vopl_out_hdmi>; > > - }; > > - }; > > - }; > > -}; > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml > > new file mode 100644 > > index 000000000000..8ff544ae0ac2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml > > @@ -0,0 +1,178 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Rockchip DWC HDMI TX Encoder > > + > > +maintainers: > > + - Mark Yao > > + > > +description: | > > + The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP > > + with a companion PHY IP. > > + > > +allOf: > > + - $ref: ../bridge/synopsys,dw-hdmi.yaml# > > + > > +properties: > > + compatible: > > + enum: > > + - rockchip,rk3228-dw-hdmi > > + - rockchip,rk3288-dw-hdmi > > + - rockchip,rk3328-dw-hdmi > > + - rockchip,rk3399-dw-hdmi > > + > > + reg: true > > + > > + reg-io-width: > > + const: 4 > > + > > + clocks: > > + minItems: 2 > > + maxItems: 5 > > + items: > > + - description: The bus clock for either AHB and APB > > + - description: The internal register configuration clock > > + - description: The HDMI CEC controller main clock > > + - description: Power for GRF IO > > + - description: External clock for some HDMI PHY > > + > > + clock-names: > > + minItems: 2 > > + maxItems: 5 > > + items: > > + - const: iahb > > + - const: isfr > > + - enum: > > + - cec > > + - grf > > + - vpll > > + - enum: > > + - cec > > + - grf > > + - vpll > > + - enum: > > + - cec > > + - grf > > + - vpll > > IIRC Rob wanted us to standardize the order of the clocks if possible, > since it's a pain to support properly here, and your description won't > match what you describe here either (and in general it's just a best > practice), so if all your DTs have the same order you should just set > that order in stone. But how do we handle the case where any of the cec, grf and vpll clocks can be set ? Assuming, for instance, that clock-names = "iahb", "isfr", "cec"; clock-names = "iahb", "isfr", "vpll"; clock-names = "iahb", "isfr", "cec", "vpll"; would all be valid. > > + ddc-i2c-bus: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: > > + The HDMI DDC bus can be connected to either a system I2C master or the > > + functionally-reduced I2C master contained in the DWC HDMI. When connected > > + to a system I2C master this property contains a phandle to that I2C > > + master controller. > > + > > + interrupts: true > > + > > + phys: > > + maxItems: 1 > > + description: The HDMI PHY > > + > > + phy-names: > > + const: hdmi > > + > > + pinctrl-0: true > > + pinctrl-1: true > > These two are already set by the tools on any schemas (up to > pinctrl-255 actually). Thank you for the information. I'll drop them. -- Regards, Laurent Pinchart