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[83.46.193.134]) by smtp.gmail.com with ESMTPSA id p3sm2049066wrq.97.2020.04.10.02.18.38 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Apr 2020 02:18:38 -0700 (PDT) From: Sergio Paracuellos To: gregkh@linuxfoundation.org Cc: neil@brown.name, driverdev-devel@linuxdriverproject.org, devicetree@vger.kernel.org, robh@kernel.org Subject: [PATCH 0/2] staging: mt7621-pci-phy: dt: bindings: convert bindings file from txt to yaml Date: Fri, 10 Apr 2020 11:18:34 +0200 Message-Id: <20200410091836.13068-1-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In order to get this driver a new chance to be properly mainlined convert bindings file into a new yaml one is missing. Previous bindings got the 'Reviewed-by' tag from Rob Herring last year in a second attempt to get this driver mainlined. See: - https://patchwork.kernel.org/patch/10878071/ In new version the use of the '#phy-cells' property has changed a bit. Before, we were using this cell to say which phy was dual ported but we were using three 'phys' and its 'phy-names' properties using instances inside the driver code making it a bit difficult. The fact of re-init registers and so on calling 'phy_init' for the phy1 was also introducing not stable clock signals on hard-resets and the kernel was hanging sometimes. Now we just use two 'phys' with two 'phy-names' nodes and we say which port is dual-ported (phy0 and phy1 share the same phy and it just use different offset in config registers to do the power on. The init process and so on shall be uniq to avoid problems so now the driver controller achieve this situation. So now, the pci controller has the following: pcie: pcie@1e140000 { compatible = "mediatek,mt7621-pci"; ... phys = <&pcie0_phy 1>, <&pcie2_phy 0>; phy-names = "pcie-phy0", "pcie-phy2"; ... } And the phys are defined as: pcie0_phy: pcie-phy@1e149000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e149000 0x0700>; #phy-cells = <1>; }; pcie2_phy: pcie-phy@1e14a000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e14a000 0x0700>; #phy-cells = <1>; }; Doing in this way we get a deterministic behaviour and stable pci clocks for both soft and hard resets and the phy driver code got simplified a lot. Rob, It would be nice to know if this is a valid approach. Thanks in advance for your time. Best regards, Sergio Paracuellos Sergio Paracuellos (2): staging: mt7621-pci-phy: dt: bindings: add mediatek,mt7621-pci-phy.yaml staging: mt7621-pci-phy: dt: bindings: remove bindings txt file .../mediatek,mt7621-pci-phy.txt | 28 --------------- .../mediatek,mt7621-pci-phy.yaml | 36 +++++++++++++++++++ 2 files changed, 36 insertions(+), 28 deletions(-) delete mode 100644 drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.txt create mode 100644 drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.yaml -- 2.25.1