* [RESEND PATCH 1/2] arm64: dts: Add SC9863A clock nodes
2020-04-14 10:16 [RESEND PATCH 0/2] add clock and emmc/sd nodes for SC9863A zhang.lyra
@ 2020-04-14 10:16 ` zhang.lyra
2020-04-14 10:16 ` [RESEND PATCH 2/2] arm64: dts: Add SC9863A emmc and sd card nodes zhang.lyra
1 sibling, 0 replies; 3+ messages in thread
From: zhang.lyra @ 2020-04-14 10:16 UTC (permalink / raw)
To: soc, Rob Herring, Mark Rutland
Cc: Arnd Bergmann, devicetree, linux-kernel, Orson Zhai, Baolin Wang,
Chunyan Zhang, Chunyan Zhang
From: Chunyan Zhang <chunyan.zhang@unisoc.com>
add clock devicetree nodes for SC9863A.
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
---
arch/arm64/boot/dts/sprd/sc9863a.dtsi | 24 ++++
arch/arm64/boot/dts/sprd/sharkl3.dtsi | 164 ++++++++++++++++++++++++++
2 files changed, 188 insertions(+)
diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi
index 2c590ca1d079..1ad6f6e95bca 100644
--- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi
+++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi
@@ -159,6 +159,30 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ ap_clk: clock-controller@21500000 {
+ compatible = "sprd,sc9863a-ap-clk";
+ reg = <0 0x21500000 0 0x1000>;
+ clocks = <&ext_32k>, <&ext_26m>;
+ clock-names = "ext-32k", "ext-26m";
+ #clock-cells = <1>;
+ };
+
+ aon_clk: clock-controller@402d0000 {
+ compatible = "sprd,sc9863a-aon-clk";
+ reg = <0 0x402d0000 0 0x1000>;
+ clocks = <&ext_26m>, <&rco_100m>,
+ <&ext_32k>, <&ext_4m>;
+ clock-names = "ext-26m", "rco-100m",
+ "ext-32k", "ext-4m";
+ #clock-cells = <1>;
+ };
+
+ mm_clk: clock-controller@60900000 {
+ compatible = "sprd,sc9863a-mm-clk";
+ reg = <0 0x60900000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
funnel@10001000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x10001000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/sprd/sharkl3.dtsi b/arch/arm64/boot/dts/sprd/sharkl3.dtsi
index 0222128b10f7..206a4afdab1c 100644
--- a/arch/arm64/boot/dts/sprd/sharkl3.dtsi
+++ b/arch/arm64/boot/dts/sprd/sharkl3.dtsi
@@ -16,6 +16,149 @@
#size-cells = <2>;
ranges;
+ ap_ahb_regs: syscon@20e00000 {
+ compatible = "sprd,sc9863a-glbregs", "syscon",
+ "simple-mfd";
+ reg = <0 0x20e00000 0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x20e00000 0x4000>;
+
+ apahb_gate: apahb-gate {
+ compatible = "sprd,sc9863a-apahb-gate";
+ reg = <0x0 0x1020>;
+ #clock-cells = <1>;
+ };
+ };
+
+ pmu_regs: syscon@402b0000 {
+ compatible = "sprd,sc9863a-glbregs", "syscon",
+ "simple-mfd";
+ reg = <0 0x402b0000 0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x402b0000 0x4000>;
+
+ pmu_gate: pmu-gate {
+ compatible = "sprd,sc9863a-pmu-gate";
+ reg = <0 0x1200>;
+ clocks = <&ext_26m>;
+ clock-names = "ext-26m";
+ #clock-cells = <1>;
+ };
+ };
+
+ aon_apb_regs: syscon@402e0000 {
+ compatible = "sprd,sc9863a-glbregs", "syscon",
+ "simple-mfd";
+ reg = <0 0x402e0000 0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x402e0000 0x4000>;
+
+ aonapb_gate: aonapb-gate {
+ compatible = "sprd,sc9863a-aonapb-gate";
+ reg = <0 0x1100>;
+ #clock-cells = <1>;
+ };
+ };
+
+ anlg_phy_g2_regs: syscon@40353000 {
+ compatible = "sprd,sc9863a-glbregs", "syscon",
+ "simple-mfd";
+ reg = <0 0x40353000 0 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x40353000 0x3000>;
+
+ pll: pll {
+ compatible = "sprd,sc9863a-pll";
+ reg = <0 0x100>;
+ clocks = <&ext_26m>;
+ clock-names = "ext-26m";
+ #clock-cells = <1>;
+ };
+ };
+
+ anlg_phy_g4_regs: syscon@40359000 {
+ compatible = "sprd,sc9863a-glbregs", "syscon",
+ "simple-mfd";
+ reg = <0 0x40359000 0 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x40359000 0x3000>;
+
+ mpll: mpll {
+ compatible = "sprd,sc9863a-mpll";
+ reg = <0 0x100>;
+ #clock-cells = <1>;
+ };
+ };
+
+ anlg_phy_g5_regs: syscon@4035c000 {
+ compatible = "sprd,sc9863a-glbregs", "syscon",
+ "simple-mfd";
+ reg = <0 0x4035c000 0 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x4035c000 0x3000>;
+
+ rpll: rpll {
+ compatible = "sprd,sc9863a-rpll";
+ reg = <0 0x100>;
+ clocks = <&ext_26m>;
+ clock-names = "ext-26m";
+ #clock-cells = <1>;
+ };
+ };
+
+ anlg_phy_g7_regs: syscon@40363000 {
+ compatible = "sprd,sc9863a-glbregs", "syscon",
+ "simple-mfd";
+ reg = <0 0x40363000 0 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x40363000 0x3000>;
+
+ dpll: dpll {
+ compatible = "sprd,sc9863a-dpll";
+ reg = <0 0x100>;
+ #clock-cells = <1>;
+ };
+ };
+
+ mm_ahb_regs: syscon@60800000 {
+ compatible = "sprd,sc9863a-glbregs", "syscon",
+ "simple-mfd";
+ reg = <0 0x60800000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x60800000 0x3000>;
+
+ mm_gate: mm-gate {
+ compatible = "sprd,sc9863a-mm-gate";
+ reg = <0 0x1100>;
+ #clock-cells = <1>;
+ };
+ };
+
+ ap_apb_regs: syscon@71300000 {
+ compatible = "sprd,sc9863a-glbregs", "syscon",
+ "simple-mfd";
+ reg = <0 0x71300000 0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x71300000 0x4000>;
+
+ apapb_gate: apapb-gate {
+ compatible = "sprd,sc9863a-apapb-gate";
+ reg = <0 0x1000>;
+ clocks = <&ext_26m>;
+ clock-names = "ext-26m";
+ #clock-cells = <1>;
+ };
+ };
+
apb@70000000 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -75,4 +218,25 @@
clock-frequency = <26000000>;
clock-output-names = "ext-26m";
};
+
+ ext_32k: ext-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ext-32k";
+ };
+
+ ext_4m: ext-4m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4000000>;
+ clock-output-names = "ext-4m";
+ };
+
+ rco_100m: rco-100m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "rco-100m";
+ };
};
--
2.20.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* [RESEND PATCH 2/2] arm64: dts: Add SC9863A emmc and sd card nodes
2020-04-14 10:16 [RESEND PATCH 0/2] add clock and emmc/sd nodes for SC9863A zhang.lyra
2020-04-14 10:16 ` [RESEND PATCH 1/2] arm64: dts: Add SC9863A clock nodes zhang.lyra
@ 2020-04-14 10:16 ` zhang.lyra
1 sibling, 0 replies; 3+ messages in thread
From: zhang.lyra @ 2020-04-14 10:16 UTC (permalink / raw)
To: soc, Rob Herring, Mark Rutland
Cc: Arnd Bergmann, devicetree, linux-kernel, Orson Zhai, Baolin Wang,
Chunyan Zhang, Chunyan Zhang
From: Chunyan Zhang <chunyan.zhang@unisoc.com>
Add emmc and sd card devicetree nodes for SC9863A.
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
---
arch/arm64/boot/dts/sprd/sc9863a.dtsi | 42 +++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi
index 1ad6f6e95bca..8cf4a6575980 100644
--- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi
+++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi
@@ -5,6 +5,7 @@
* Copyright (C) 2019, Unisoc Inc.
*/
+#include <dt-bindings/clock/sprd,sc9863a-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "sharkl3.dtsi"
@@ -543,5 +544,46 @@
};
};
};
+
+ ap-ahb {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ sdio0: sdio@20300000 {
+ compatible = "sprd,sdhci-r11";
+ reg = <0 0x20300000 0 0x1000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+
+ clock-names = "sdio", "enable";
+ clocks = <&aon_clk CLK_SDIO0_2X>,
+ <&apahb_gate CLK_SDIO0_EB>;
+ assigned-clocks = <&aon_clk CLK_SDIO0_2X>;
+ assigned-clock-parents = <&rpll CLK_RPLL_390M>;
+
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+ };
+
+ sdio3: sdio@20600000 {
+ compatible = "sprd,sdhci-r11";
+ reg = <0 0x20600000 0 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+
+ clock-names = "sdio", "enable";
+ clocks = <&aon_clk CLK_EMMC_2X>,
+ <&apahb_gate CLK_EMMC_EB>;
+ assigned-clocks = <&aon_clk CLK_EMMC_2X>;
+ assigned-clock-parents = <&rpll CLK_RPLL_390M>;
+
+ bus-width = <8>;
+ non-removable;
+ no-sdio;
+ no-sd;
+ cap-mmc-hw-reset;
+ };
+ };
};
};
--
2.20.1
^ permalink raw reply related [flat|nested] 3+ messages in thread