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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id d61sm5640680otb.53.2020.04.14.10.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Apr 2020 10:38:39 -0700 (PDT) Received: (nullmailer pid 2638 invoked by uid 1000); Tue, 14 Apr 2020 17:38:38 -0000 Date: Tue, 14 Apr 2020 12:38:38 -0500 From: Rob Herring To: Ansuel Smith Cc: Andy Gross , Bjorn Andersson , Kishon Vijay Abraham I , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 2/2] devicetree: bindings: phy: Document dwc3 qcom phy Message-ID: <20200414173838.GA29176@bogus> References: <20200403002608.946-1-ansuelsmth@gmail.com> <20200403002608.946-2-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200403002608.946-2-ansuelsmth@gmail.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Apr 03, 2020 at 02:26:05AM +0200, Ansuel Smith wrote: > Document dwc3 qcom phy hs and ss phy bindings needed to correctly > inizialize and use usb on ipq806x SoC > > Signed-off-by: Ansuel Smith > --- > .../bindings/phy/qcom,dwc3-hs-usb-phy.yaml | 65 +++++++++++++++++++ > .../bindings/phy/qcom,dwc3-ss-usb-phy.yaml | 65 +++++++++++++++++++ > 2 files changed, 130 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-phy.yaml > create mode 100644 Documentation/devicetree/bindings/phy/qcom,dwc3-ss-usb-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-phy.yaml > new file mode 100644 > index 000000000000..0bb59e3c2ab8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,dwc3-hs-usb-phy.yaml > @@ -0,0 +1,65 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,dwc3-hs-usb-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm DWC3 HS PHY CONTROLLER > + > +maintainers: > + - Ansuel Smith > + > +description: > + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer > + controllers. Each DWC3 PHY controller should have its own node. > + > +properties: > + compatible: > + const: qcom,dwc3-hs-usb-phy > + > + "#phy-cells": > + const: 0 > + > + regmap: > + maxItems: 1 > + description: phandle to usb3 dts definition > + > + clocks: > + minItems: 1 > + maxItems: 2 > + > + clock-names: > + minItems: 1 > + maxItems: 2 > + description: | > + - "ref" Is required > + - "xo" Optional external reference clock > + items: > + - const: ref > + - const: xo > + > +required: > + - compatible > + - "#phy-cells" > + - regmap > + - clocks > + - clock-names > + > +examples: > + - | > + #include > + > + hs_phy_0: hs_phy_0 { > + compatible = "qcom,dwc3-hs-usb-phy"; > + regmap = <&usb3_0>; If the registers for the phy are part of 'qcom,dwc3' then make this node a child of it. > + clocks = <&gcc USB30_0_UTMI_CLK>; > + clock-names = "ref"; > + #phy-cells = <0>; > + }; > + > + usb3_0: usb3@110f8800 { > + compatible = "qcom,dwc3", "syscon"; > + reg = <0x110f8800 0x8000>; > + > + /* ... */ Incomplete examples should or will fail validation. > + };