From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14BFCC2BA19 for ; Wed, 15 Apr 2020 09:48:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F036320775 for ; Wed, 15 Apr 2020 09:48:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2895824AbgDOJsu (ORCPT ); Wed, 15 Apr 2020 05:48:50 -0400 Received: from relay10.mail.gandi.net ([217.70.178.230]:55945 "EHLO relay10.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2895800AbgDOJss (ORCPT ); Wed, 15 Apr 2020 05:48:48 -0400 Received: from localhost (lfbn-lyo-1-9-35.w86-202.abo.wanadoo.fr [86.202.105.35]) (Authenticated sender: alexandre.belloni@bootlin.com) by relay10.mail.gandi.net (Postfix) with ESMTPSA id 22ED924000F; Wed, 15 Apr 2020 09:48:44 +0000 (UTC) From: Alexandre Belloni To: Daniel Lezcano Cc: Thomas Gleixner , Nicolas Ferre , Sebastian Andrzej Siewior , kamel.bouhara@bootlin.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Alexandre Belloni Subject: [PATCH v2 0/9] clocksource/drivers/timer-atmel-tcb: add sama5d2 support Date: Wed, 15 Apr 2020 11:48:17 +0200 Message-Id: <20200415094826.132562-1-alexandre.belloni@bootlin.com> X-Mailer: git-send-email 2.25.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This series mainly adds sama5d2 support where we need to avoid using clock index 0 because that clock is never enabled by the driver. There is also a rework of the 32khz clock handling so it is not used for clockevents on 32 bit counter because the increased rate improves the resolution and doesn't have any drawback with that counter width. This replaces a patch that has been carried in the linux-rt tree for a while. Changes in v2: - Rebased on v5.7-rc1 - Moved the binding documentation to its proper place - Added back the atmel,tcb-timer child node documentation Alexandre Belloni (8): dt-bindings: atmel-tcb: convert bindings to json-schema dt-bindings: microchip: atmel,at91rm9200-tcb: add sama5d2 compatible ARM: dts: at91: sama5d2: add TCB GCLK clocksource/drivers/timer-atmel-tcb: rework 32khz clock selection clocksource/drivers/timer-atmel-tcb: fill tcb_config clocksource/drivers/timer-atmel-tcb: stop using the 32kHz for clockevents clocksource/drivers/timer-atmel-tcb: allow selecting first divider clocksource/drivers/timer-atmel-tcb: add sama5d2 support Kamel Bouhara (1): ARM: at91: add atmel tcb capabilities .../devicetree/bindings/mfd/atmel-tcb.txt | 56 --------- .../soc/microchip/atmel,at91rm9200-tcb.yaml | 113 ++++++++++++++++++ .../bindings/timer/atmel,tcb-timer.yaml | 51 ++++++++ arch/arm/boot/dts/sama5d2.dtsi | 12 +- drivers/clocksource/timer-atmel-tcb.c | 101 +++++++++------- include/soc/at91/atmel_tcb.h | 5 + 6 files changed, 233 insertions(+), 105 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-tcb.txt create mode 100644 Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml create mode 100644 Documentation/devicetree/bindings/timer/atmel,tcb-timer.yaml -- 2.25.2