From: Rob Herring <robh@kernel.org>
To: Dinh Nguyen <dinguyen@kernel.org>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, sboyd@kernel.org,
mturquette@baylibre.com, mark.rutland@arm.com
Subject: Re: [PATCHv6 4/5] dt-bindings: documentation: add clock bindings information for Agilex
Date: Wed, 15 Apr 2020 09:40:16 -0500 [thread overview]
Message-ID: <20200415144016.GA26244@bogus> (raw)
In-Reply-To: <20200406160418.27476-5-dinguyen@kernel.org>
On Mon, Apr 06, 2020 at 11:04:17AM -0500, Dinh Nguyen wrote:
> Document the Agilex clock bindings, and add the clock header file. The
> clock header is an enumeration of all the different clocks on the Agilex
> platform.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> v6: fix build error by adding descriptions for clocks and reg in
> properties
> v5: update license to GPL-2.0-only
> Add additionalProperties
> Add clock input for clkmgr
> v4: really fix build error(comment formatting was wrong)
> v3: address comments from Stephen Boyd
> fix build error(tab removed in line 37)
> renamed to intel,agilex.yaml
> v2: convert original document to YAML
> ---
> .../bindings/clock/intel,agilex.yaml | 46 ++++++++++++
> include/dt-bindings/clock/agilex-clock.h | 70 +++++++++++++++++++
> 2 files changed, 116 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml
> create mode 100644 include/dt-bindings/clock/agilex-clock.h
>
> diff --git a/Documentation/devicetree/bindings/clock/intel,agilex.yaml b/Documentation/devicetree/bindings/clock/intel,agilex.yaml
> new file mode 100644
> index 000000000000..83bca2661ec3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/intel,agilex.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: GPL-2.0-only
Dual license new bindings:
(GPL-2.0-only OR BSD-2-Clause)
With that:
Reviewed-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2020-04-15 14:40 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-06 16:04 [PATCHv6 0/5] clk: agilex: add clock driver Dinh Nguyen
2020-04-06 16:04 ` [PATCHv6 1/5] clk: socfpga: stratix10: use new parent data scheme Dinh Nguyen
2020-04-06 16:04 ` [PATCHv6 2/5] clk: socfpga: remove clk_ops enable/disable methods Dinh Nguyen
2020-04-06 16:04 ` [PATCHv6 3/5] clk: socfpga: add const to _ops data structures Dinh Nguyen
2020-04-06 16:04 ` [PATCHv6 4/5] dt-bindings: documentation: add clock bindings information for Agilex Dinh Nguyen
2020-04-15 14:40 ` Rob Herring [this message]
2020-04-06 16:04 ` [PATCHv6 5/5] clk: socfpga: agilex: add clock driver for the Agilex platform Dinh Nguyen
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