* [PATCH v2 1/3] dt-bindings: arm: qcom: Add sdm630 and sdm660 SoCs
2020-04-17 1:26 [PATCH v2 0/3] Add initial support for SDM660/630 SoCs Alexey Minnekhanov
@ 2020-04-17 1:26 ` Alexey Minnekhanov
2020-04-17 1:26 ` [PATCH v2 2/3] arm64: dts: qcom: Add SDM660 SoC support Alexey Minnekhanov
2020-04-17 1:26 ` [PATCH v2 3/3] arm64: dts: qcom: Add Xiaomi Redmi Note 7 (lavender) Alexey Minnekhanov
2 siblings, 0 replies; 4+ messages in thread
From: Alexey Minnekhanov @ 2020-04-17 1:26 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Mark Rutland,
devicetree, linux-arm-msm, ~postmarketos/upstreaming
Cc: Alexey Minnekhanov, Alexey Minnekhanov
Add a SoC strings for the Qualcomm SDM630 and SDM660 SoCs.
Also document the new xiaomi,lavender compatible used in
a device tree binding.
Signed-off-by: Alexey Minnekhanov <alexey.min@gmail.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 64ddae3bd39f..6031aee0f5a8 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -37,6 +37,8 @@ description: |
msm8994
msm8996
sc7180
+ sdm630
+ sdm660
sdm845
The 'board' element must be one of the following strings:
@@ -153,6 +155,11 @@ properties:
- qcom,sc7180-idp
- const: qcom,sc7180
+ - items:
+ - enum:
+ - xiaomi,lavender
+ - const: qcom,sdm660
+
- items:
- enum:
- qcom,ipq6018-cp01-c1
--
2.25.3
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v2 2/3] arm64: dts: qcom: Add SDM660 SoC support
2020-04-17 1:26 [PATCH v2 0/3] Add initial support for SDM660/630 SoCs Alexey Minnekhanov
2020-04-17 1:26 ` [PATCH v2 1/3] dt-bindings: arm: qcom: Add sdm630 and sdm660 SoCs Alexey Minnekhanov
@ 2020-04-17 1:26 ` Alexey Minnekhanov
2020-04-17 1:26 ` [PATCH v2 3/3] arm64: dts: qcom: Add Xiaomi Redmi Note 7 (lavender) Alexey Minnekhanov
2 siblings, 0 replies; 4+ messages in thread
From: Alexey Minnekhanov @ 2020-04-17 1:26 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Mark Rutland,
devicetree, linux-arm-msm, ~postmarketos/upstreaming
Cc: Alexey Minnekhanov, Craig Tatlor, Alexey Minnekhanov
From: Craig Tatlor <ctatlor97@gmail.com>
Initial device tree support for Qualcomm SDM660 SoC.
SDM660 is based off MSM8998 and uses some of its drivers.
SDM630/636 are based off SDM660 SoC and they are pin
and software compatible.
The device tree is based on the CAF 4.4 kernel tree.
Features:
* CPU nodes
* Timer nodes
* Interrupt controller
* Global Clock Controller
* Top Level Mode Multiplexer (pin controller)
* UART node
This is inspired by and based on the work of Craig Tatlor in
https://patchwork.kernel.org/patch/10563667/
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
Signed-off-by: Alexey Minnekhanov <alexey.min@gmail.com>
---
arch/arm64/boot/dts/qcom/sdm660.dtsi | 372 +++++++++++++++++++++++++++
1 file changed, 372 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi
new file mode 100644
index 000000000000..4abbdd03d1e7
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi
@@ -0,0 +1,372 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018, Craig Tatlor.
+ * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ clock-output-names = "xo_board";
+ };
+
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32764>;
+ clock-output-names = "sleep_clk";
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ L1_I_100: l1-icache {
+ compatible = "cache";
+ };
+ L1_D_100: l1-dcache {
+ compatible = "cache";
+ };
+ };
+
+ CPU1: cpu@101 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ next-level-cache = <&L2_1>;
+ L1_I_101: l1-icache {
+ compatible = "cache";
+ };
+ L1_D_101: l1-dcache {
+ compatible = "cache";
+ };
+ };
+
+ CPU2: cpu@102 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ next-level-cache = <&L2_1>;
+ L1_I_102: l1-icache {
+ compatible = "cache";
+ };
+ L1_D_102: l1-dcache {
+ compatible = "cache";
+ };
+ };
+
+ CPU3: cpu@103 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ next-level-cache = <&L2_1>;
+ L1_I_103: l1-icache {
+ compatible = "cache";
+ };
+ L1_D_103: l1-dcache {
+ compatible = "cache";
+ };
+ };
+
+ CPU4: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <640>;
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ L1_I_0: l1-icache {
+ compatible = "cache";
+ };
+ L1_D_0: l1-dcache {
+ compatible = "cache";
+ };
+ };
+
+ CPU5: cpu@1 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <640>;
+ next-level-cache = <&L2_0>;
+ L1_I_1: l1-icache {
+ compatible = "cache";
+ };
+ L1_D_1: l1-dcache {
+ compatible = "cache";
+ };
+ };
+
+ CPU6: cpu@2 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <640>;
+ next-level-cache = <&L2_0>;
+ L1_I_2: l1-icache {
+ compatible = "cache";
+ };
+ L1_D_2: l1-dcache {
+ compatible = "cache";
+ };
+ };
+
+ CPU7: cpu@3 {
+ device_type = "cpu";
+ compatible = "qcom,kryo260";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <640>;
+ next-level-cache = <&L2_0>;
+ L1_I_3: l1-icache {
+ compatible = "cache";
+ };
+ L1_D_3: l1-dcache {
+ compatible = "cache";
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sdm660";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ reg = <0x00100000 0x94000>;
+ };
+
+ tlmm: pinctrl@3100000 {
+ compatible = "qcom,sdm660-pinctrl";
+ reg = <0x03100000 0x400000>,
+ <0x03500000 0x400000>,
+ <0x03900000 0x400000>;
+ reg-names = "south", "center", "north";
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ gpio-ranges = <&tlmm 0 0 114>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart_console_active: uart_console_active {
+ pinmux {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
+ };
+
+ pinconf {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ spmi_bus: spmi@800f000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0800f000 0x1000>,
+ <0x08400000 0x1000000>,
+ <0x09400000 0x1000000>,
+ <0x0a400000 0x220000>,
+ <0x0800a000 0x3000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
+ blsp1_uart2: serial@c170000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0c170000 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ timer@17920000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x17920000 0x1000>;
+
+ frame@17921000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17921000 0x1000>,
+ <0x17922000 0x1000>;
+ };
+
+ frame@17923000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17923000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17924000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17924000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17925000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17925000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17926000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17926000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17927000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17927000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17928000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17928000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x17a00000 0x10000>,
+ <0x17b00000 0x100000>;
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
--
2.25.3
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v2 3/3] arm64: dts: qcom: Add Xiaomi Redmi Note 7 (lavender)
2020-04-17 1:26 [PATCH v2 0/3] Add initial support for SDM660/630 SoCs Alexey Minnekhanov
2020-04-17 1:26 ` [PATCH v2 1/3] dt-bindings: arm: qcom: Add sdm630 and sdm660 SoCs Alexey Minnekhanov
2020-04-17 1:26 ` [PATCH v2 2/3] arm64: dts: qcom: Add SDM660 SoC support Alexey Minnekhanov
@ 2020-04-17 1:26 ` Alexey Minnekhanov
2 siblings, 0 replies; 4+ messages in thread
From: Alexey Minnekhanov @ 2020-04-17 1:26 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Mark Rutland,
devicetree, linux-arm-msm, ~postmarketos/upstreaming
Cc: Alexey Minnekhanov, Alexey Minnekhanov
This adds the initial device tree support for Xiaomi
Redmi Note 7 (codename lavender) phone. It is based on
SDM660 SoC. Currently it can be booted into initrd with
a shell over UART and you can also get kernel boot logs
from a pstore-ramoops.
Signed-off-by: Alexey Minnekhanov <alexey.min@gmail.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 46 +++++++++++++++++++
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index cc103f7020fd..0f2c33d611df 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
new file mode 100644
index 000000000000..76533e8b2092
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "sdm660.dtsi"
+
+/ {
+ model = "Xiaomi Redmi Note 7";
+ compatible = "xiaomi,lavender", "qcom,sdm660";
+
+ aliases {
+ serial0 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ramoops@a0000000 {
+ compatible = "ramoops";
+ reg = <0x0 0xa0000000 0x0 0x400000>;
+ console-size = <0x20000>;
+ record-size = <0x20000>;
+ ftrace-size = <0x0>;
+ pmsg-size = <0x20000>;
+ };
+ };
+};
+
+&blsp1_uart2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart_console_active>;
+};
+
+&tlmm {
+ gpio-reserved-ranges = <8 4>;
+};
--
2.25.3
^ permalink raw reply related [flat|nested] 4+ messages in thread