From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B33FEC3A5A0 for ; Sun, 19 Apr 2020 22:28:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9B15820B1F for ; Sun, 19 Apr 2020 22:28:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726048AbgDSW2V (ORCPT ); Sun, 19 Apr 2020 18:28:21 -0400 Received: from mga05.intel.com ([192.55.52.43]:59485 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725848AbgDSW2U (ORCPT ); Sun, 19 Apr 2020 18:28:20 -0400 IronPort-SDR: YdqpwMrfgpoC84ppwJ97RGM0CqlkCXFCH76UccdgMLk/WnQv3PDyaJZXetlzZFYyxzYvbWbHKr UNtpFWpYt30w== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2020 15:28:20 -0700 IronPort-SDR: Nh+Dex8K9ftQjDSvavCHtA2y3a9nVX58784fZWSVhNqHos1DyHm21UfAcqen4FhIVAQ9CFSSxP PEoGt9ZMnosw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,404,1580803200"; d="scan'208";a="289824346" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.40]) by fmsmga002.fm.intel.com with ESMTP; 19 Apr 2020 15:28:15 -0700 Received: from andy by smile with local (Exim 4.93) (envelope-from ) id 1jQIQD-001v9r-Qw; Mon, 20 Apr 2020 01:28:17 +0300 Date: Mon, 20 Apr 2020 01:28:17 +0300 From: Andy Shevchenko To: "Ramuthevar,Vadivel MuruganX" Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, arnd@arndb.de, brendanhiggins@google.com, tglx@linutronix.de, boris.brezillon@collabora.com, anders.roxell@linaro.org, masonccyang@mxic.com.tw, piotrs@cadence.com, robh+dt@kernel.org, linux-mips@vger.kernel.org, hauke.mehrtens@intel.com, qi-ming.wu@intel.com, cheol.yong.kim@intel.com Subject: Re: [PATCH v2 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Message-ID: <20200419222817.GK185537@smile.fi.intel.com> References: <20200417082147.43384-1-vadivel.muruganx.ramuthevar@linux.intel.com> <20200417082147.43384-3-vadivel.muruganx.ramuthevar@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200417082147.43384-3-vadivel.muruganx.ramuthevar@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Apr 17, 2020 at 04:21:47PM +0800, Ramuthevar,Vadivel MuruganX wrote: > From: Ramuthevar Vadivel Murugan > > This patch adds the new IP of Nand Flash Controller(NFC) support > on Intel's Lightning Mountain(LGM) SoC. > > DMA is used for burst data transfer operation, also DMA HW supports > aligned 32bit memory address and aligned data access by default. > DMA burst of 8 supported. Data register used to support the read/write > operation from/to device. > > NAND controller driver implements ->exec_op() to replace legacy hooks, > these specific call-back method to execute NAND operations. I guess untested version slipped into mailing list... See below why. ... > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include Do you need this? > +#include > +#include > +#include > +#include > +#include > +#include Basically, do you need all of them? And maybe keep them in order? ... > +static int lgm_dma_init(struct device *dev, struct lgm_nand_host *lgm_host) > +{ > + int ret; > + > + /* Prepare for TX DMA: */ > + lgm_host->dma_tx = dma_request_chan(dev, "tx"); > + if (IS_ERR(lgm_host->dma_tx)) { > + ret = PTR_ERR(lgm_host->dma_tx); > + dev_err(dev, "can't get the TX DMA channel, error %d!\n", ret); > + goto err; > + } > + > + /* Prepare for RX: */ > + lgm_host->dma_rx = dma_request_chan(dev, "rx"); > + if (IS_ERR(lgm_host->dma_rx)) { > + ret = PTR_ERR(lgm_host->dma_rx); > + dev_err(dev, "can't get the RX DMA channel, error %d\n", ret); I suspect this error path hasn't been tested. I don't see where tx channel freeing is happening. > + goto err; > + } > + > + return 0; > +err: > + return ret; Redundant label. > +} ... > + res = devm_platform_ioremap_resource_byname(pdev, lgm_host->cs_name); > + lgm_host->nandaddr_va = res; > + nandaddr_pa = res->start; > + if (IS_ERR(lgm_host->nandaddr_va)) > + return PTR_ERR(lgm_host->nandaddr_va); I'm wondering what is this. How is it even compile? -- With Best Regards, Andy Shevchenko