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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id r26sm1344769pfq.75.2020.04.22.22.11.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Apr 2020 22:11:36 -0700 (PDT) Date: Wed, 22 Apr 2020 22:12:03 -0700 From: Bjorn Andersson To: Mike Leach Cc: agross@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, suzuki.poulose@arm.com Subject: Re: [PATCH] dt-bindings: qcom: Add CTI options for qcom msm8916 Message-ID: <20200423051203.GA2166963@builder.lan> References: <20200415201230.15766-1-mike.leach@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200415201230.15766-1-mike.leach@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed 15 Apr 13:12 PDT 2020, Mike Leach wrote: > Adds system and CPU bound CTI definitions for Qualcom msm8916 platform > (Dragonboard DB410C). > System CTIs 2-11 are omitted as no information available at present. > > Tested on Linux 5.7-rc1. > > Signed-off-by: Mike Leach > Reviewed-by: Mathieu Poirier > Acked-by: Suzuki K Poulose Thanks Mike, I adjusted subject and have applied the patch towards 5.8. Regards, Bjorn > --- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 85 +++++++++++++++++++++++++-- > 1 file changed, 81 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index a88a15f2352b..194d5e45f4e5 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > > / { > interrupt-parent = <&intc>; > @@ -1424,7 +1425,7 @@ > cpu = <&CPU3>; > }; > > - etm@85c000 { > + etm0: etm@85c000 { > compatible = "arm,coresight-etm4x", "arm,primecell"; > reg = <0x85c000 0x1000>; > > @@ -1443,7 +1444,7 @@ > }; > }; > > - etm@85d000 { > + etm1: etm@85d000 { > compatible = "arm,coresight-etm4x", "arm,primecell"; > reg = <0x85d000 0x1000>; > > @@ -1462,7 +1463,7 @@ > }; > }; > > - etm@85e000 { > + etm2: etm@85e000 { > compatible = "arm,coresight-etm4x", "arm,primecell"; > reg = <0x85e000 0x1000>; > > @@ -1481,7 +1482,7 @@ > }; > }; > > - etm@85f000 { > + etm3: etm@85f000 { > compatible = "arm,coresight-etm4x", "arm,primecell"; > reg = <0x85f000 0x1000>; > > @@ -1500,6 +1501,82 @@ > }; > }; > > + /* System CTIs */ > + /* CTI 0 - TMC connections */ > + cti@810000 { > + compatible = "arm,coresight-cti", "arm,primecell"; > + reg = <0x810000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + }; > + > + /* CTI 1 - TPIU connections */ > + cti@811000 { > + compatible = "arm,coresight-cti", "arm,primecell"; > + reg = <0x811000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + }; > + > + /* CTIs 2-11 - no information - not instantiated */ > + > + /* Core CTIs; CTIs 12-15 */ > + /* CTI - CPU-0 */ > + cti@858000 { > + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", > + "arm,primecell"; > + reg = <0x858000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + > + cpu = <&CPU0>; > + arm,cs-dev-assoc = <&etm0>; > + > + }; > + > + /* CTI - CPU-1 */ > + cti@859000 { > + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", > + "arm,primecell"; > + reg = <0x859000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + > + cpu = <&CPU1>; > + arm,cs-dev-assoc = <&etm1>; > + }; > + > + /* CTI - CPU-2 */ > + cti@85a000 { > + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", > + "arm,primecell"; > + reg = <0x85a000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + > + cpu = <&CPU2>; > + arm,cs-dev-assoc = <&etm2>; > + }; > + > + /* CTI - CPU-3 */ > + cti@85b000 { > + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", > + "arm,primecell"; > + reg = <0x85b000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + > + cpu = <&CPU3>; > + arm,cs-dev-assoc = <&etm3>; > + }; > + > + > venus: video-codec@1d00000 { > compatible = "qcom,msm8916-venus"; > reg = <0x01d00000 0xff000>; > -- > 2.17.1 >