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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id q142sm4938585oic.44.2020.04.28.08.58.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Apr 2020 08:58:47 -0700 (PDT) Received: (nullmailer pid 2205 invoked by uid 1000); Tue, 28 Apr 2020 15:58:46 -0000 Date: Tue, 28 Apr 2020 10:58:46 -0500 From: Rob Herring To: Ansuel Smith Cc: Andy Gross , Bjorn Andersson , Kishon Vijay Abraham I , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 2/2] devicetree: bindings: phy: Document ipq806x dwc3 qcom phy Message-ID: <20200428155846.GA29778@bogus> References: <20200415210729.9618-1-ansuelsmth@gmail.com> <20200415210729.9618-2-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200415210729.9618-2-ansuelsmth@gmail.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Apr 15, 2020 at 11:07:27PM +0200, Ansuel Smith wrote: > Document dwc3 qcom phy hs and ss phy bindings needed to correctly > inizialize and use usb on ipq806x SoC. > > Signed-off-by: Ansuel Smith > --- > v3: > * Use explicit reg instead of regmap > > .../bindings/phy/qcom,ipq806x-usb-phy-hs.yaml | 58 +++++++++++++++ > .../bindings/phy/qcom,ipq806x-usb-phy-ss.yaml | 70 +++++++++++++++++++ > 2 files changed, 128 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml > new file mode 100644 > index 000000000000..c019de7478e3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER > + > +maintainers: > + - Ansuel Smith > + > +description: > + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer > + controllers used in ipq806x. Each DWC3 PHY controller should have its > + own node. > + > +properties: > + compatible: > + const: qcom,ipq806x-usb-phy-hs > + > + "#phy-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 2 > + > + clock-names: > + minItems: 1 > + maxItems: 2 > + description: | > + - "ref" Is required > + - "xo" Optional external reference clock > + items: > + - const: ref > + - const: xo > + > +required: > + - compatible > + - "#phy-cells" > + - reg > + - clocks > + - clock-names > + > +examples: > + - | > + #include > + > + hs_phy_0: phy@110f8800 { > + compatible = "qcom,ipq806x-usb-phy-hs"; > + reg = <0x110f8800 0x30>; > + clocks = <&gcc USB30_0_UTMI_CLK>; > + clock-names = "ref"; > + #phy-cells = <0>; > + }; > diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml > new file mode 100644 > index 000000000000..29a7d3aed289 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-ss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER > + > +maintainers: > + - Ansuel Smith > + > +description: > + DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer > + controllers used in ipq806x. Each DWC3 PHY controller should have its > + own node. > + > +properties: > + compatible: > + const: qcom,ipq806x-usb-phy-ss > + > + "#phy-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 2 > + > + clock-names: > + minItems: 1 > + maxItems: 2 > + description: | > + - "ref" Is required > + - "xo" Optional external reference clock > + items: > + - const: ref > + - const: xo > + > + rx_eq: qcom,rx-eq > + maxItems: 1 Is this an array? > + description: Override value for rx_eq. Default is 4. > + > + tx_deamp_3_5db: qcom,tx-deamp-3-5db > + maxItems: 1 > + description: Override value for transmit preemphasis. Default is 23. default: 23 > + > + mpll: qcom,mpll > + maxItems: 1 > + description: Override value for mpll. Default is 0. Constraints? default: 0 > + > +required: > + - compatible > + - "#phy-cells" > + - reg > + - clocks > + - clock-names > + > +examples: > + - | > + #include > + > + ss_phy_0: phy@110f8830 { > + compatible = "qcom,ipq806x-usb-phy-ss"; > + reg = <0x110f8830 0x30>; > + clocks = <&gcc USB30_0_MASTER_CLK>; > + clock-names = "ref"; > + #phy-cells = <0>; > + }; > -- > 2.25.1 >