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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id 85sm653166oie.17.2020.05.05.08.56.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2020 08:56:12 -0700 (PDT) Received: (nullmailer pid 28089 invoked by uid 1000); Tue, 05 May 2020 15:56:11 -0000 Date: Tue, 5 May 2020 10:56:11 -0500 From: Rob Herring To: Alim Akhtar Cc: devicetree@vger.kernel.org, linux-scsi@vger.kernel.org, krzk@kernel.org, avri.altman@wdc.com, martin.petersen@oracle.com, kwmad.kim@samsung.com, stanley.chu@mediatek.com, cang@codeaurora.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v7 06/10] dt-bindings: phy: Document Samsung UFS PHY bindings Message-ID: <20200505155611.GA23690@bogus> References: <20200426173024.63069-1-alim.akhtar@samsung.com> <20200426173024.63069-7-alim.akhtar@samsung.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20200426173024.63069-7-alim.akhtar@samsung.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Sun, Apr 26, 2020 at 11:00:20PM +0530, Alim Akhtar wrote: > This patch documents Samsung UFS PHY device tree bindings > > Signed-off-by: Alim Akhtar > Tested-by: Paweł Chmiel > --- > .../bindings/phy/samsung,ufs-phy.yaml | 74 +++++++++++++++++++ > 1 file changed, 74 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml > new file mode 100644 > index 000000000000..352d5dda320d > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml > @@ -0,0 +1,74 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Samsung SoC series UFS PHY Device Tree Bindings > + > +maintainers: > + - Alim Akhtar > + > +properties: > + "#phy-cells": > + const: 0 > + > + compatible: > + enum: > + - samsung,exynos7-ufs-phy > + > + reg: > + maxItems: 1 > + description: PHY base register address Can drop the description. Doesn't add anything special. > + > + reg-names: > + items: > + - const: phy-pma > + > + clocks: > + items: > + - description: PLL reference clock > + - description: symbol clock for input symbol ( rx0-ch0 symbol clock) > + - description: symbol clock for input symbol ( rx1-ch1 symbol clock) > + - description: symbol clock for output symbol ( tx0 symbol clock) > + > + clock-names: > + items: > + - const: ref_clk > + - const: rx1_symbol_clk > + - const: rx0_symbol_clk > + - const: tx0_symbol_clk > + > + samsung,pmu-syscon: > + $ref: '/schemas/types.yaml#/definitions/phandle' > + description: phandle for PMU system controller interface, used to > + control pmu registers bits for ufs m-phy > + > +required: > + - "#phy-cells" > + - compatible > + - reg > + - reg-names > + - clocks > + - clock-names > + - samsung,pmu-syscon Add: additionalProperties: false With that, Reviewed-by: Rob Herring > + > +examples: > + - | > + #include > + > + ufs_phy: ufs-phy@15571800 { > + compatible = "samsung,exynos7-ufs-phy"; > + reg = <0x15571800 0x240>; > + reg-names = "phy-pma"; > + samsung,pmu-syscon = <&pmu_system_controller>; > + #phy-cells = <0>; > + clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>, > + <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>, > + <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>, > + <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>; > + clock-names = "ref_clk", "rx1_symbol_clk", > + "rx0_symbol_clk", "tx0_symbol_clk"; > + > + }; > +... > -- > 2.17.1 >