* [PATCH v3 2/5] dt-bindings: net: mdio-gpio: add compatible for microchip,mdio-smi0 [not found] <20200508154343.6074-1-m.grzeschik@pengutronix.de> @ 2020-05-08 15:43 ` Michael Grzeschik 2020-05-09 16:57 ` Andrew Lunn ` (2 more replies) 2020-05-08 15:43 ` [PATCH v3 5/5] dt-bindings: net: dsa: document additional Microchip KSZ8863/8873 switch Michael Grzeschik 1 sibling, 3 replies; 6+ messages in thread From: Michael Grzeschik @ 2020-05-08 15:43 UTC (permalink / raw) To: andrew; +Cc: netdev, f.fainelli, davem, kernel, devicetree Microchip SMI0 Mode is a special mode, where the MDIO Read/Write commands are part of the PHY Address and the OP Code is always 0. We add the compatible for this special mode of the bitbanged mdio driver. Cc: devicetree@vger.kernel.org Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> --- Documentation/devicetree/bindings/net/mdio-gpio.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/mdio-gpio.txt b/Documentation/devicetree/bindings/net/mdio-gpio.txt index 8dbcf8295c6c9c..4d91a36c5cf503 100644 --- a/Documentation/devicetree/bindings/net/mdio-gpio.txt +++ b/Documentation/devicetree/bindings/net/mdio-gpio.txt @@ -2,6 +2,7 @@ MDIO on GPIOs Currently defined compatibles: - virtual,gpio-mdio +- microchip,mdio-smi0 MDC and MDIO lines connected to GPIO controllers are listed in the gpios property as described in section VIII.1 in the following order: -- 2.26.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: net: mdio-gpio: add compatible for microchip,mdio-smi0 2020-05-08 15:43 ` [PATCH v3 2/5] dt-bindings: net: mdio-gpio: add compatible for microchip,mdio-smi0 Michael Grzeschik @ 2020-05-09 16:57 ` Andrew Lunn 2020-05-09 17:16 ` Florian Fainelli 2020-05-19 18:21 ` Rob Herring 2 siblings, 0 replies; 6+ messages in thread From: Andrew Lunn @ 2020-05-09 16:57 UTC (permalink / raw) To: Michael Grzeschik; +Cc: netdev, f.fainelli, davem, kernel, devicetree On Fri, May 08, 2020 at 05:43:40PM +0200, Michael Grzeschik wrote: > Microchip SMI0 Mode is a special mode, where the MDIO Read/Write > commands are part of the PHY Address and the OP Code is always 0. We add > the compatible for this special mode of the bitbanged mdio driver. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: net: mdio-gpio: add compatible for microchip,mdio-smi0 2020-05-08 15:43 ` [PATCH v3 2/5] dt-bindings: net: mdio-gpio: add compatible for microchip,mdio-smi0 Michael Grzeschik 2020-05-09 16:57 ` Andrew Lunn @ 2020-05-09 17:16 ` Florian Fainelli 2020-05-19 18:21 ` Rob Herring 2 siblings, 0 replies; 6+ messages in thread From: Florian Fainelli @ 2020-05-09 17:16 UTC (permalink / raw) To: Michael Grzeschik, andrew; +Cc: netdev, davem, kernel, devicetree On 5/8/2020 8:43 AM, Michael Grzeschik wrote: > Microchip SMI0 Mode is a special mode, where the MDIO Read/Write > commands are part of the PHY Address and the OP Code is always 0. We add > the compatible for this special mode of the bitbanged mdio driver. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> -- Florian ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: net: mdio-gpio: add compatible for microchip,mdio-smi0 2020-05-08 15:43 ` [PATCH v3 2/5] dt-bindings: net: mdio-gpio: add compatible for microchip,mdio-smi0 Michael Grzeschik 2020-05-09 16:57 ` Andrew Lunn 2020-05-09 17:16 ` Florian Fainelli @ 2020-05-19 18:21 ` Rob Herring 2 siblings, 0 replies; 6+ messages in thread From: Rob Herring @ 2020-05-19 18:21 UTC (permalink / raw) To: Michael Grzeschik; +Cc: kernel, andrew, f.fainelli, devicetree, netdev, davem On Fri, 8 May 2020 17:43:40 +0200, Michael Grzeschik wrote: > Microchip SMI0 Mode is a special mode, where the MDIO Read/Write > commands are part of the PHY Address and the OP Code is always 0. We add > the compatible for this special mode of the bitbanged mdio driver. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> > --- > Documentation/devicetree/bindings/net/mdio-gpio.txt | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 5/5] dt-bindings: net: dsa: document additional Microchip KSZ8863/8873 switch [not found] <20200508154343.6074-1-m.grzeschik@pengutronix.de> 2020-05-08 15:43 ` [PATCH v3 2/5] dt-bindings: net: mdio-gpio: add compatible for microchip,mdio-smi0 Michael Grzeschik @ 2020-05-08 15:43 ` Michael Grzeschik 2020-05-09 16:57 ` Andrew Lunn 1 sibling, 1 reply; 6+ messages in thread From: Michael Grzeschik @ 2020-05-08 15:43 UTC (permalink / raw) To: andrew; +Cc: netdev, f.fainelli, davem, kernel, devicetree, Rob Herring It is a 3-Port 10/100 Ethernet Switch. One CPU-Port and two Switch-Ports. Cc: devicetree@vger.kernel.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> --- v1 -> v3: - nothing changes - already Acked-by Rob Herring Documentation/devicetree/bindings/net/dsa/ksz.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/ksz.txt b/Documentation/devicetree/bindings/net/dsa/ksz.txt index 95e91e84151c33..a5d71862f53cbc 100644 --- a/Documentation/devicetree/bindings/net/dsa/ksz.txt +++ b/Documentation/devicetree/bindings/net/dsa/ksz.txt @@ -8,6 +8,8 @@ Required properties: - "microchip,ksz8765" - "microchip,ksz8794" - "microchip,ksz8795" + - "microchip,ksz8863" + - "microchip,ksz8873" - "microchip,ksz9477" - "microchip,ksz9897" - "microchip,ksz9896" -- 2.26.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 5/5] dt-bindings: net: dsa: document additional Microchip KSZ8863/8873 switch 2020-05-08 15:43 ` [PATCH v3 5/5] dt-bindings: net: dsa: document additional Microchip KSZ8863/8873 switch Michael Grzeschik @ 2020-05-09 16:57 ` Andrew Lunn 0 siblings, 0 replies; 6+ messages in thread From: Andrew Lunn @ 2020-05-09 16:57 UTC (permalink / raw) To: Michael Grzeschik Cc: netdev, f.fainelli, davem, kernel, devicetree, Rob Herring On Fri, May 08, 2020 at 05:43:43PM +0200, Michael Grzeschik wrote: > It is a 3-Port 10/100 Ethernet Switch. One CPU-Port and two > Switch-Ports. > > Cc: devicetree@vger.kernel.org > Acked-by: Rob Herring <robh@kernel.org> > Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew ^ permalink raw reply [flat|nested] 6+ messages in thread
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[not found] <20200508154343.6074-1-m.grzeschik@pengutronix.de>
2020-05-08 15:43 ` [PATCH v3 2/5] dt-bindings: net: mdio-gpio: add compatible for microchip,mdio-smi0 Michael Grzeschik
2020-05-09 16:57 ` Andrew Lunn
2020-05-09 17:16 ` Florian Fainelli
2020-05-19 18:21 ` Rob Herring
2020-05-08 15:43 ` [PATCH v3 5/5] dt-bindings: net: dsa: document additional Microchip KSZ8863/8873 switch Michael Grzeschik
2020-05-09 16:57 ` Andrew Lunn
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