From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFBC7C2D0FA for ; Wed, 13 May 2020 10:30:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C26AB206CC for ; Wed, 13 May 2020 10:30:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729731AbgEMKau (ORCPT ); Wed, 13 May 2020 06:30:50 -0400 Received: from foss.arm.com ([217.140.110.172]:42672 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732694AbgEMKat (ORCPT ); Wed, 13 May 2020 06:30:49 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 082B8D6E; Wed, 13 May 2020 03:30:49 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E2AB93F305; Wed, 13 May 2020 03:30:47 -0700 (PDT) From: Andre Przywara To: Rob Herring , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland Subject: [PATCH v3 14/20] arm64: dts: fvp: Fix SMMU DT node Date: Wed, 13 May 2020 11:30:10 +0100 Message-Id: <20200513103016.130417-15-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200513103016.130417-1-andre.przywara@arm.com> References: <20200513103016.130417-1-andre.przywara@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SMMU name in the RevC FVP DT file was not fully binding compliant. Adjust the node name to match the binding's list of allowed names, also shuffle the order of the interrupts to comply with the expected order. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/arm/fvp-base-revc.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts index 0cf96ceff431..b8a21092db4d 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -172,14 +172,14 @@ dma-coherent; }; - smmu: smmu@2b400000 { + smmu: iommu@2b400000 { compatible = "arm,smmu-v3"; reg = <0x0 0x2b400000 0x0 0x100000>; interrupts = , + , , - , - ; - interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; dma-coherent; #iommu-cells = <1>; msi-parent = <&its 0x10000>; -- 2.17.1