Re: [PATCH v4 06/10] dt-bindings: mtd: update STM32 FMC2 NAND controller documentation

[Rob Herring <robh@kernel.org>]

On Wed, May 06, 2020 at 11:11:15AM +0200, Christophe Kerello wrote:
> These bindings can be used on SOCs where the FMC2 NAND controller is
> in standalone. In case that the FMC2 embeds 2 controllers (an external
> bus controller and a raw NAND controller), the register base and the
> clock will be defined in the parent node. It is the reason why the
> register base address and the clock are now optional.
> 
> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
> ---
>  .../devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml   | 19 ++++++++++---------
>  1 file changed, 10 insertions(+), 9 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml
> index b059267..68fac1a 100644
> --- a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml
> +++ b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml
> @@ -18,13 +18,15 @@ properties:
>  
>    reg:
>      items:
> -      - description: Registers
> +      - description: Registers (optional)

The only thing that can be optional are the last entries. You have to do 
a 'oneOf' with 6 entries and 7 entries.

And where's your new compatible string for this different h/w?

>        - description: Chip select 0 data
>        - description: Chip select 0 command
>        - description: Chip select 0 address space
>        - description: Chip select 1 data
>        - description: Chip select 1 command
>        - description: Chip select 1 address space
> +    minItems: 6
> +    maxItems: 7
>  
>    interrupts:
>      maxItems: 1
> @@ -61,7 +63,6 @@ required:
>    - compatible
>    - reg
>    - interrupts
> -  - clocks
>  
>  examples:
>    - |
> @@ -77,13 +78,13 @@ examples:
>              <0x81000000 0x1000>,
>              <0x89010000 0x1000>,
>              <0x89020000 0x1000>;
> -            interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> -            dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
> -                   <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
> -                   <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
> -            dma-names = "tx", "rx", "ecc";
> -            clocks = <&rcc FMC_K>;
> -            resets = <&rcc FMC_R>;
> +      interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> +      dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
> +             <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
> +             <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
> +      dma-names = "tx", "rx", "ecc";
> +      clocks = <&rcc FMC_K>;
> +      resets = <&rcc FMC_R>;
>        #address-cells = <1>;
>        #size-cells = <0>;
>  
> -- 
> 1.9.1
>