From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61E81C433DF for ; Mon, 18 May 2020 07:17:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3DD372070A for ; Mon, 18 May 2020 07:17:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="fjBow3uM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727799AbgERHRg (ORCPT ); Mon, 18 May 2020 03:17:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726939AbgERHRg (ORCPT ); Mon, 18 May 2020 03:17:36 -0400 Received: from mail-pl1-x642.google.com (mail-pl1-x642.google.com [IPv6:2607:f8b0:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5464EC061A0C for ; Mon, 18 May 2020 00:17:36 -0700 (PDT) Received: by mail-pl1-x642.google.com with SMTP id x10so3863650plr.4 for ; Mon, 18 May 2020 00:17:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FkqkwhOV2kALvGF4g6te/6iFt9fJLPzgBLr4Dh309IQ=; b=fjBow3uM65SvUJ2AOHJJF2RYAe1lI+uMVzeMus+VEQSA7o48J55Hweb0r2UJFpeB0T 9waYZtXRQIT4/7D4lcEhgEJRAZ9cGEWCQkfD639aX6NHxGacYe2YvTpUTpelxbHDqVF6 UVShJY/n1l0yjqbjGYw36vT4b11nKKwigo28Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FkqkwhOV2kALvGF4g6te/6iFt9fJLPzgBLr4Dh309IQ=; b=VJhK052ePNTDaPOhUHVspSIAj7fU1wtmhE6IGWR4oJg5tjqOBs7+xMYI4izKKl1owD VIsNBmYXlFMZ9uzpwyNm4X9eBnJe5yqwRODgojCN/A3vSlZY0KSBSgLwk2YMajyFEqc7 aa9LaROLJabF2/h1WTcybw+fOXAbBwUOu+CimvhSmGQtrvQZyUr1VF8Ui+HPs5e3iOEf Zd1JFCYuiokXW9a1e2jkxwSGPfs1sxDebaxIaoVlLC+O4eTvgD1xgt2hmge6xg2DzGf6 LX0beXh1u2+BOjXlSN3Q/lYYHoR60Ihg11UHa8pz8zQ225pgwYqm+DdeWjcylFiWNGw0 Q9XA== X-Gm-Message-State: AOAM531Jd40pH0zmtFM+iMN9jp4FSNnXKNzwYNE2tHRLkGQ5Omo7RLMI /l1S5I0dccK0sx1UyTtyZo5gwg== X-Google-Smtp-Source: ABdhPJwkE7QUQ0Fwv/p5TijHgeFhyYyl+mN1cy8yiU0qSBUVm0/vkOGOi++LpzUO5bQoLZtjnb7uHw== X-Received: by 2002:a17:90a:b10f:: with SMTP id z15mr16669746pjq.188.1589786255806; Mon, 18 May 2020 00:17:35 -0700 (PDT) Received: from pmalani2.mtv.corp.google.com ([2620:15c:202:201:476b:691:abc3:38db]) by smtp.gmail.com with ESMTPSA id 30sm6928590pgp.38.2020.05.18.00.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2020 00:17:34 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org Cc: heikki.krogerus@linux.intel.com, Prashant Malani , Heikki Krogerus , Benson Leung , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), Enric Balletbo i Serra , Guenter Roeck , Rob Herring Subject: [PATCH v2 2/2] platform/chrome: typec: Register Type C switches Date: Mon, 18 May 2020 00:17:06 -0700 Message-Id: <20200518071707.161843-2-pmalani@chromium.org> X-Mailer: git-send-email 2.26.2.761.g0e0b3e54be-goog In-Reply-To: <20200518071707.161843-1-pmalani@chromium.org> References: <20200518071707.161843-1-pmalani@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Register Type C mux and switch handles, when provided via firmware bindings. These will allow the cros-ec-typec driver, and also alternate mode drivers to configure connected Muxes correctly, according to PD information retrieved from the Chrome OS EC. Signed-off-by: Prashant Malani Reviewed-by: Heikki Krogerus --- Changes in v2: - Changed dev_info prints to dev_dbg. drivers/platform/chrome/cros_ec_typec.c | 47 +++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c index 66b8d21092af..6e79f917314b 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #define DRV_NAME "cros-ec-typec" @@ -25,6 +27,9 @@ struct cros_typec_port { struct typec_partner *partner; /* Port partner PD identity info. */ struct usb_pd_identity p_identity; + struct typec_switch *ori_sw; + struct typec_mux *mux; + struct usb_role_switch *role_sw; }; /* Platform-specific data for the Chrome OS EC Type C controller. */ @@ -84,6 +89,40 @@ static int cros_typec_parse_port_props(struct typec_capability *cap, return 0; } +static int cros_typec_get_switch_handles(struct cros_typec_port *port, + struct fwnode_handle *fwnode, + struct device *dev) +{ + port->mux = fwnode_typec_mux_get(fwnode, NULL); + if (IS_ERR(port->mux)) { + dev_dbg(dev, "Mux handle not found.\n"); + goto mux_err; + } + + port->ori_sw = fwnode_typec_switch_get(fwnode); + if (IS_ERR(port->ori_sw)) { + dev_dbg(dev, "Orientation switch handle not found.\n"); + goto ori_sw_err; + } + + port->role_sw = fwnode_usb_role_switch_get(fwnode); + if (IS_ERR(port->role_sw)) { + dev_dbg(dev, "USB role switch handle not found.\n"); + goto role_sw_err; + } + + return 0; + +role_sw_err: + usb_role_switch_put(port->role_sw); +ori_sw_err: + typec_switch_put(port->ori_sw); +mux_err: + typec_mux_put(port->mux); + + return -ENODEV; +} + static void cros_unregister_ports(struct cros_typec_data *typec) { int i; @@ -91,6 +130,9 @@ static void cros_unregister_ports(struct cros_typec_data *typec) for (i = 0; i < typec->num_ports; i++) { if (!typec->ports[i]) continue; + usb_role_switch_put(typec->ports[i]->role_sw); + typec_switch_put(typec->ports[i]->ori_sw); + typec_mux_put(typec->ports[i]->mux); typec_unregister_port(typec->ports[i]->port); } } @@ -153,6 +195,11 @@ static int cros_typec_init_ports(struct cros_typec_data *typec) ret = PTR_ERR(cros_port->port); goto unregister_ports; } + + ret = cros_typec_get_switch_handles(cros_port, fwnode, dev); + if (ret) + dev_dbg(dev, "No switch control for port %d\n", + port_num); } return 0; -- 2.26.2.761.g0e0b3e54be-goog