From: Joakim Zhang <qiangqing.zhang@nxp.com>
To: john.garry@huawei.com, will@kernel.org, mark.rutland@arm.com,
robh+dt@kernel.org, shawnguo@kernel.org
Cc: linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH V2 1/3] bindings: perf: imx8_ddr: add identifier property
Date: Wed, 20 May 2020 10:56:17 +0800 [thread overview]
Message-ID: <20200520025619.687-2-qiangqing.zhang@nxp.com> (raw)
In-Reply-To: <20200520025619.687-1-qiangqing.zhang@nxp.com>
Add "identifier" property for DDR Perf which used to identity system pmu.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
index 7822a806ea0a..ebb9a40094c5 100644
--- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
+++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
@@ -12,6 +12,8 @@ Required properties:
- interrupts: single interrupt
generated by the control block
+- identifier: identify system pmu
+
Example:
ddr-pmu@5c020000 {
@@ -19,4 +21,5 @@ Example:
reg = <0x5c020000 0x10000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ identifier = "i.mx8mm";
};
--
2.17.1
next prev parent reply other threads:[~2020-05-20 2:59 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-20 2:56 [PATCH V2 0/3] perf/imx_ddr: Add system PMU support Joakim Zhang
2020-05-20 2:56 ` Joakim Zhang [this message]
2020-05-20 2:56 ` [PATCH V2 2/3] perf/imx_ddr: Add system PMU identifier for userspace Joakim Zhang
2020-05-20 7:41 ` Will Deacon
2020-05-20 2:56 ` [PATCH V2 3/3] arm64: dts: imx8/8mm/8mn/8mq: add identifier for DDR perf Joakim Zhang
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