From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB922C433E0 for ; Wed, 20 May 2020 08:49:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9047207ED for ; Wed, 20 May 2020 08:49:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="V5P8TwdK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726691AbgETItF (ORCPT ); Wed, 20 May 2020 04:49:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726546AbgETItF (ORCPT ); Wed, 20 May 2020 04:49:05 -0400 Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EEB7C05BD43 for ; Wed, 20 May 2020 01:49:05 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id b190so1225692pfg.6 for ; Wed, 20 May 2020 01:49:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=mUXoHCk9YjTWtIe6lbZRmuzsCBfcD819p2whO3KZzec=; b=V5P8TwdKayVbTIZwm1h3TmhwoplB3ufnXPirbcvqxIZEaxZVWo0JRlVQXvn8r/K9gs 4RCoyH9TJpBmE8kcM8SF1Pri5yYNd/oHodStSUbHGHkVSz6HoibzfFJ1V8C6qAr2rdlA gF1hsua1hK1WBDyQjqDBj3rPex1e8ZH7Wtt1XGHM76n13q9hSyWaiCsdTMRjFGTIGeOL q6bTFWs4FODgiQLavsdRlt2teB+gCiMl+V58t7MsCN2HkyJMn17q9jhBEgB/BZHNsDed wN5elR8SYIg3OOyqNlmAHfTXdA8I6mGY0s+tSsP0WDOHVScKLX87TVdsjjA82uKJqzrQ ItTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=mUXoHCk9YjTWtIe6lbZRmuzsCBfcD819p2whO3KZzec=; b=hTb91I5lBMCYc2FgZnd5XxrPhXOAwADDuDu9bNM22Lj0uS2QglxbGU2pcPL10juiQx 9L8ZCgF6yiDnLXwh7XW5/v7ECfRW0erjQjsd9IMBa3g6jsGd/IrGpIorJDfb//pVJC6o nRXWPPa7pN3dMunx/FNDRImh/7OjJsajTemzgU2v2O7wmHY67g5YpUf1w19ilUlUJJMp wgPpLr4GrVerw2wKZCQpEqaY1agm2mBAgJznEM1/oq0IWqrsvAnNVfLUoRMXVwOkSXQz vomb4zoVmre+BkTe6gu/b1+47FoH6ygtYBuGxRBOpfsG7J2TR0OAp+wRounxTbkgeR+c aSHA== X-Gm-Message-State: AOAM533VEQLOQfmvQCfP4fagF7ZY+OjufTx+NmUzt8tThk+4o/GUpp6O 9B6aWeauCjN6qrEXH3xbHWoC X-Google-Smtp-Source: ABdhPJyq90ZITiiPWo8tMvFxVbmDXvkTW65XmUrhBPoNPkXK2t+uMDsUzjGi4u3kCRRn4t6FSPQIhQ== X-Received: by 2002:aa7:9e92:: with SMTP id p18mr3257038pfq.195.1589964544634; Wed, 20 May 2020 01:49:04 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:91e:dd0a:7c30:1f7e:ebdb:aa2a]) by smtp.gmail.com with ESMTPSA id a5sm1629332pfk.210.2020.05.20.01.49.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2020 01:49:03 -0700 (PDT) From: Manivannan Sadhasivam To: jassisinghbrar@gmail.com, robh+dt@kernel.org Cc: bjorn.andersson@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 0/3] Add Qualcomm IPCC driver support Date: Wed, 20 May 2020 14:18:51 +0530 Message-Id: <20200520084854.19729-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.26.GIT MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hello, This series adds mailbox driver support for Qualcomm Inter Processor Communications Controller (IPCC) block found in MSM chipsets. This block is used to route interrupts between modems, DSPs and APSS (Application Processor Subsystem). The driver is modeled as a mailbox+irqchip driver. The irqchip part helps in receiving the interrupts from the IPCC clients such as modems, DSPs, PCI-E etc... and forwards them to respective entities in APSS. On the other hand, the mailbox part is used to send interrupts to the IPCC clients from the entities of APSS. This series is tested on SM8250-MTP board. Thanks, Mani Changes in v3: * Added Bjorn's review tags * Few changes to DT binding as suggested by Rob Changes in v2: * Moved from soc/ to mailbox/ * Switched to static mbox channels * Some misc cleanups Manivannan Sadhasivam (3): dt-bindings: mailbox: Add devicetree binding for Qcom IPCC mailbox: Add support for Qualcomm IPCC MAINTAINERS: Add entry for Qualcomm IPCC driver .../bindings/mailbox/qcom-ipcc.yaml | 80 +++++ MAINTAINERS | 8 + drivers/mailbox/Kconfig | 10 + drivers/mailbox/Makefile | 2 + drivers/mailbox/qcom-ipcc.c | 286 ++++++++++++++++++ include/dt-bindings/mailbox/qcom-ipcc.h | 33 ++ 6 files changed, 419 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml create mode 100644 drivers/mailbox/qcom-ipcc.c create mode 100644 include/dt-bindings/mailbox/qcom-ipcc.h -- 2.26.GIT