From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85549C433E0 for ; Fri, 22 May 2020 07:31:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6D26C2073B for ; Fri, 22 May 2020 07:31:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728821AbgEVHbN (ORCPT ); Fri, 22 May 2020 03:31:13 -0400 Received: from elvis.franken.de ([193.175.24.41]:34218 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728707AbgEVHbN (ORCPT ); Fri, 22 May 2020 03:31:13 -0400 Received: from uucp (helo=alpha) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1jc28x-0003HE-03; Fri, 22 May 2020 09:30:59 +0200 Received: by alpha.franken.de (Postfix, from userid 1000) id 6D443C015D; Fri, 22 May 2020 09:28:37 +0200 (CEST) Date: Fri, 22 May 2020 09:28:37 +0200 From: Thomas Bogendoerfer To: Serge Semin Cc: Serge Semin , Alexey Malahov , Paul Burton , Ralf Baechle , Arnd Bergmann , Rob Herring , devicetree@vger.kernel.org, Jiaxun Yang , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Huacai Chen , Paul Cercueil , Masahiro Yamada , Zhou Yanjie , WANG Xuerui , =?utf-8?B?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= , YunQiang Su , Liangliang Huang , Thomas Gleixner , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 06/13] mips: Add CP0 Write Merge config support Message-ID: <20200522072837.GD7331@alpha.franken.de> References: <20200521140725.29571-1-Sergey.Semin@baikalelectronics.ru> <20200521140725.29571-7-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200521140725.29571-7-Sergey.Semin@baikalelectronics.ru> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, May 21, 2020 at 05:07:17PM +0300, Serge Semin wrote: > CP0 config register may indicate whether write-through merging > is allowed. Currently there are two types of the merging available: > SysAD Valid and Full modes. Whether each of them are supported by > the core is implementation dependent. Moreover whether the ability > to change the mode also depends on the chip family instance. Taking > into account all of this we created a dedicated mm_config() method > to detect and enable merging if it's supported. It is called for > MIPS-type processors at CPU-probe stage and attempts to detect whether > the write merging is available. If it's known to be supported and > switchable, then switch on the full mode. Otherwise just perform the > CP0.Config.MM field analysis. > > In addition there are platforms like InterAptiv/ProAptiv, which do have > the MM bit field set by default, but having write-through cacheing > unsupported makes write-merging also unsupported. In this case we just > ignore the MM field value. > > Co-developed-by: Alexey Malahov > Signed-off-by: Alexey Malahov > Signed-off-by: Serge Semin > Cc: Thomas Bogendoerfer > Cc: Paul Burton > Cc: Ralf Baechle > Cc: Arnd Bergmann > Cc: Rob Herring > Cc: devicetree@vger.kernel.org > --- > arch/mips/include/asm/cpu-features.h | 8 +++++ > arch/mips/include/asm/cpu.h | 4 ++- > arch/mips/include/asm/mipsregs.h | 3 ++ > arch/mips/kernel/cpu-probe.c | 48 ++++++++++++++++++++++++++++ > 4 files changed, 62 insertions(+), 1 deletion(-) applied to mips-next. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]