From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Serge Semin <fancer.lancer@gmail.com>,
Vinod Koul <vkoul@kernel.org>, Viresh Kumar <vireshk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Arnd Bergmann <arnd@arndb.de>, Rob Herring <robh+dt@kernel.org>,
<linux-mips@vger.kernel.org>, <devicetree@vger.kernel.org>,
<dmaengine@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 09/10] dmaengine: dw: Introduce max burst length hw config
Date: Thu, 28 May 2020 18:40:22 +0300 [thread overview]
Message-ID: <20200528154022.3reghhjcd4dnsr3g@mobilestation> (raw)
In-Reply-To: <20200528145224.GT1634618@smile.fi.intel.com>
On Thu, May 28, 2020 at 05:52:24PM +0300, Andy Shevchenko wrote:
> On Wed, May 27, 2020 at 01:50:20AM +0300, Serge Semin wrote:
> > IP core of the DW DMA controller may be synthesized with different
> > max burst length of the transfers per each channel. According to Synopsis
> > having the fixed maximum burst transactions length may provide some
> > performance gain. At the same time setting up the source and destination
> > multi size exceeding the max burst length limitation may cause a serious
> > problems. In our case the DMA transaction just hangs up. In order to fix
> > this lets introduce the max burst length platform config of the DW DMA
> > controller device and don't let the DMA channels configuration code
> > exceed the burst length hardware limitation.
> >
> > Note the maximum burst length parameter can be detected either in runtime
> > from the DWC parameter registers or from the dedicated DT property.
> > Depending on the IP core configuration the maximum value can vary from
> > channel to channel so by overriding the channel slave max_burst capability
> > we make sure a DMA consumer will get the channel-specific max burst
> > length.
>
> ...
>
> > static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
> > {
> > + struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
> >
>
> Perhaps,
>
> /* DesignWare DMA supports burst value from 0 */
> caps->min_burst = 0;
Regarding min_burst being zero. I don't fully understand what it means.
It means no burst or burst with minimum length or what?
In fact DW DMA burst length starts from 1. Remember the burst-length run-time
parameter we were arguing about? Anyway the driver makes sure that both
0 and 1 requested burst length are setup as burst length of 1 in the
CTLx.SRC_MSIZE, CTLx.DST_MSIZE fields.
I agree with the rest of your comments below.
-Sergey
>
> > + caps->max_burst = dwc->max_burst;
> > }
>
> ...
>
> > + *maxburst = clamp(*maxburst, 0U, dwc->max_burst);
>
> Shouldn't we do the same for iDMA 32-bit? Thus, perhaps do it in the core.c?
>
> > *maxburst = *maxburst > 1 ? fls(*maxburst) - 2 : 0;
>
> > + if (!of_property_read_u32_array(np, "snps,max-burst-len", mb,
> > + nr_channels)) {
> > + for (tmp = 0; tmp < nr_channels; tmp++)
> > + pdata->max_burst[tmp] = mb[tmp];
>
> I think we may read directly to the array. This ugly loops were introduced due
> to type mismatch. (See below)
>
> > + } else {
> > + for (tmp = 0; tmp < nr_channels; tmp++)
> > + pdata->max_burst[tmp] = DW_DMA_MAX_BURST;
> > + }
>
> And this will be effectively memset32().
>
> > unsigned char nr_masters;
> > unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
> > unsigned char multi_block[DW_DMA_MAX_NR_CHANNELS];
> > + unsigned int max_burst[DW_DMA_MAX_NR_CHANNELS];
>
> I think we have to stop with this kind of types and use directly what is in the
> properties, i.e.
>
> u32 max_burst[...];
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
next prev parent reply other threads:[~2020-05-28 15:40 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-26 22:50 [PATCH v3 00/10] dmaengine: dw: Take Baikal-T1 SoC DW DMAC peculiarities into account Serge Semin
2020-05-26 22:50 ` [PATCH v3 01/10] dt-bindings: dma: dw: Convert DW DMAC to DT binding Serge Semin
2020-05-26 22:50 ` [PATCH v3 02/10] dt-bindings: dma: dw: Add max burst transaction length property Serge Semin
2020-05-26 22:50 ` [PATCH v3 03/10] dmaengine: Introduce min burst length capability Serge Semin
2020-05-28 14:21 ` Andy Shevchenko
2020-05-26 22:50 ` [PATCH v3 04/10] dmaengine: Introduce max SG list entries capability Serge Semin
2020-05-28 14:22 ` Andy Shevchenko
2020-05-26 22:50 ` [PATCH v3 05/10] dmaengine: Introduce DMA-device device_caps callback Serge Semin
2020-05-28 14:42 ` Andy Shevchenko
2020-05-28 15:19 ` Serge Semin
2020-05-28 20:34 ` Andy Shevchenko
2020-05-26 22:50 ` [PATCH v3 06/10] dmaengine: dw: Take HC_LLP flag into account for noLLP auto-config Serge Semin
2020-05-26 22:50 ` [PATCH v3 07/10] dmaengine: dw: Set DMA device max segment size parameter Serge Semin
2020-05-26 22:50 ` [PATCH v3 08/10] dmaengine: dw: Add dummy device_caps callback Serge Semin
2020-05-28 14:53 ` Andy Shevchenko
2020-05-28 15:27 ` Serge Semin
2020-05-28 20:29 ` Andy Shevchenko
2020-05-28 20:34 ` Serge Semin
2020-05-26 22:50 ` [PATCH v3 09/10] dmaengine: dw: Introduce max burst length hw config Serge Semin
2020-05-28 14:52 ` Andy Shevchenko
2020-05-28 15:40 ` Serge Semin [this message]
2020-05-28 19:53 ` Serge Semin
2020-05-28 20:38 ` Andy Shevchenko
2020-05-26 22:50 ` [PATCH v3 10/10] dmaengine: dw: Initialize max_sg_nents with nollp flag Serge Semin
2020-05-28 14:56 ` Andy Shevchenko
2020-05-28 15:50 ` Serge Semin
2020-05-28 20:31 ` Andy Shevchenko
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