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From: Dinh Nguyen <dinguyen@kernel.org>
To: linux-clk@vger.kernel.org
Cc: dinguyen@kernel.org, devicetree@vger.kernel.org,
	mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org
Subject: [PATCH 3/3] clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk
Date: Tue, 16 Jun 2020 15:24:17 -0500	[thread overview]
Message-ID: <20200616202417.14376-3-dinguyen@kernel.org> (raw)
In-Reply-To: <20200616202417.14376-1-dinguyen@kernel.org>

Preliminary documentation documented the mpu_l2ram_clk, but since then,
the mpu_l2ram_clk is no longer documented. It's now referred to as
mpu_ccu_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 drivers/clk/socfpga/clk-agilex.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
index 1b2e0ad01b24..8fb12cbe0208 100644
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -252,7 +252,7 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = {
 	  0, 0, 0, 0, 0x30, 0, 0},
 	{ AGILEX_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x24,
 	  0, 0, 0, 0, 0, 0, 4},
-	{ AGILEX_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x24,
+	{ AGILEX_MPU_CCU_CLK, "mpu_ccu_clk", "mpu_clk", NULL, 1, 0, 0x24,
 	  0, 0, 0, 0, 0, 0, 2},
 	{ AGILEX_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x24,
 	  1, 0x44, 0, 2, 0, 0, 0},
-- 
2.17.1


  parent reply	other threads:[~2020-06-16 20:24 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-16 20:24 [PATCH 1/3] dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK Dinh Nguyen
2020-06-16 20:24 ` [PATCH 2/3] clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk Dinh Nguyen
2020-06-20  2:37   ` Stephen Boyd
2020-06-16 20:24 ` Dinh Nguyen [this message]
2020-06-20  2:37   ` [PATCH 3/3] clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk Stephen Boyd
2020-06-20  2:37 ` [PATCH 1/3] dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK Stephen Boyd

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