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[216.228.112.21]) by smtp.gmail.com with ESMTPSA id j36sm3305919pgj.39.2020.06.16.23.25.15 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Jun 2020 23:25:16 -0700 (PDT) Date: Tue, 16 Jun 2020 23:24:58 -0700 From: Nicolin Chen To: Shengjiu Wang Cc: timur@kernel.org, Xiubo.Lee@gmail.com, festevam@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, lgirdwood@gmail.com, robh+dt@kernel.org, devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/2] ASoC: fsl_spdif: Add support for imx6sx platform Message-ID: <20200617062457.GA6411@Asurada-Nvidia> References: <53a969a83999de91f3ff2809d78335c3f0cc1ee3.1592368322.git.shengjiu.wang@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <53a969a83999de91f3ff2809d78335c3f0cc1ee3.1592368322.git.shengjiu.wang@nxp.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Jun 17, 2020 at 12:30:17PM +0800, Shengjiu Wang wrote: > The one difference on imx6sx platform is that the root clock > is shared with ASRC module, so we add a new flags > "shared_root_clock" which means the root clock is independent, "shared" means "not independent", against "independent" ;) > then we will not do the clk_set_rate and clk_round_rate to avoid > impact ASRC module usage. > > As add a new flags, we include the soc specific data struct. > > Signed-off-by: Shengjiu Wang Can add this once fixing the remaining comments: Reviewed-by: Nicolin Chen > +static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, > + int clk) Can actually merge into single line as kernel has 100-character limit now, though 80-char is still preferable for a good coding style. But I think this one wouldn't be too bad at all. > @@ -421,7 +456,7 @@ static int spdif_set_sample_rate(struct snd_pcm_substream *substream, > sysclk_df = spdif_priv->sysclk_df[rate]; > > /* Don't mess up the clocks from other modules */ We can drop this comments now as it's out-of-date and the name of the new helper function is straightforward enough. > - if (clk != STC_TXCLK_SPDIF_ROOT) > + if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk)) > goto clk_set_bypass; > > /* The S/PDIF block needs a clock of 64 * fs * txclk_df */