From: Rob Herring <robh@kernel.org>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: Re: [PATCH 06/38] dt-bindings: display: tegra: Document display-hub
Date: Wed, 17 Jun 2020 16:55:06 -0600 [thread overview]
Message-ID: <20200617225506.GC2975260@bogus> (raw)
In-Reply-To: <20200612141903.2391044-7-thierry.reding@gmail.com>
On Fri, Jun 12, 2020 at 04:18:31PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Tegra186 and later have an additional component in the display pipeline
> called the display hub. Document the bindings which were missing.
I'd rather this be after the conversion or I'm reviewing it twice.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../display/tegra/nvidia,tegra20-host1x.txt | 50 +++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
> index 47319214b5f6..2cf3cc4893da 100644
> --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
> @@ -297,6 +297,56 @@ of the following host1x client modules:
> - reset-names: Must include the following entries:
> - vic
>
> +- display-hub: display controller hub
> + Required properties:
> + - compatible: "nvidia,tegra<chip>-display"
> + - reg: Physical base address and length of the controller's registers.
> + - interrupts: The interrupt outputs from the controller.
> + - clocks: Must contain an entry for each entry in clock-names.
> + See ../clocks/clock-bindings.txt for details.
> + - clock-names: Must include the following entries:
> + - disp
> + - dsc
> + - hub
> + - resets: Must contain an entry for each entry in reset-names.
> + See ../reset/reset.txt for details.
> + - reset-names: Must include the following entries:
> + - misc
> + - wgrp0
> + - wgrp1
> + - wgrp2
> + - wgrp3
> + - wgrp4
> + - wgrp5
> + - power-domains: A list of phandle and specifiers identifying the power
> + domains that the display hub is part of.
> + - ranges: Range of registers used for the display controllers.
> +
> + Each subnode of the display hub represents one of the display controllers
> + available:
> +
> + - display: display controller
> + - compatible: "nvidia,tegra<chip>-dc"
> + - reg: Physical base address and length of the controller's registers.
> + - interrupts: The interrupt outputs from the controller.
> + - clocks: Must contain an entry for each entry in clock-names.
> + See ../clocks/clock-bindings.txt for details.
> + - clock-names: Must include the following entries:
> + - dc
> + - resets: Must contain an entry for each entry in reset-names.
> + See ../reset/reset.txt for details.
> + - reset-names: Must include the following entries:
> + - dc
> + - power-domains: A list of phandle and specifiers that identify the power
> + domains that this display controller is part of.
> + - iommus: A phandle and specifier identifying the SMMU master interface of
> + this display controller.
> + - nvidia,outputs: A list of phandles of outputs that this display
> + controller can drive.
Seems like an OF graph should describe this?
> + - nvidia,head: The number of the display controller head. This is used to
> + setup the various types of output to receive video data from the given
> + head.
Not really clear what this is...
> +
> Example:
>
> / {
> --
> 2.24.1
>
next prev parent reply other threads:[~2020-06-17 22:55 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-12 14:18 [PATCH 00/38] dt-bindings: json-schema conversions and cleanups Thierry Reding
2020-06-12 14:18 ` [PATCH 01/38] dt-bindings: interrupt-controller: arm,gic: Add compatible for Tegra186 AGIC Thierry Reding
2020-06-12 14:18 ` [PATCH 02/38] dt-bindings: memory: nvidia: Mark memory controller as interconnect provider Thierry Reding
2020-06-12 14:18 ` [PATCH 03/38] dt-bindings: memory: Increase number of reg entries on Tegra194 Thierry Reding
2020-06-12 14:18 ` [PATCH 04/38] dt-bindings: firmware: Convert Tegra186 BPMP bindings to json-schema Thierry Reding
2020-06-17 22:49 ` Rob Herring
2020-06-12 14:18 ` [PATCH 05/38] dt-bindings: firmware: tegra186-bpmp: Document interconnect paths Thierry Reding
2020-06-17 22:50 ` Rob Herring
2020-06-12 14:18 ` [PATCH 06/38] dt-bindings: display: tegra: Document display-hub Thierry Reding
2020-06-17 22:55 ` Rob Herring [this message]
2020-06-18 10:27 ` Thierry Reding
2020-06-18 18:17 ` Rob Herring
2020-06-19 6:45 ` Thierry Reding
2020-06-12 14:18 ` [PATCH 07/38] dt-bindings: display: tegra: Convert to json-schema Thierry Reding
2020-06-12 15:54 ` Dmitry Osipenko
2020-06-16 14:51 ` Thierry Reding
2020-06-17 23:13 ` Rob Herring
2020-06-18 14:16 ` Thierry Reding
2020-06-18 15:23 ` Rob Herring
2020-06-19 8:08 ` Thierry Reding
2020-06-12 14:18 ` [PATCH 08/38] dt-bindings: display: tegra: Document interconnect paths Thierry Reding
2020-06-12 15:52 ` Dmitry Osipenko
2020-06-16 14:47 ` Thierry Reding
2020-06-12 14:18 ` [PATCH 09/38] dt-bindings: gpu: tegra: Convert to json-schema Thierry Reding
2020-06-18 2:29 ` Rob Herring
2020-06-12 14:18 ` [PATCH 10/38] dt-bindings: gpu: tegra: Document interconnect paths Thierry Reding
2020-06-12 14:18 ` [PATCH 11/38] dt-bindings: mmc: tegra: Convert to json-schema Thierry Reding
2020-06-12 14:18 ` [PATCH 12/38] dt-bindings: mmc: tegra: Document interconnect paths Thierry Reding
2020-06-12 14:18 ` [PATCH 13/38] dt-bindings: pci: tegra: Convert to json-schema Thierry Reding
2020-06-12 14:18 ` [PATCH 14/38] dt-bindings: pci: tegra: Document interconnect paths Thierry Reding
2020-06-12 14:18 ` [PATCH 15/38] dt-bindings: sound: tegra: hda: Convert to json-schema Thierry Reding
2020-06-12 14:18 ` [PATCH 16/38] dt-bindings: sound: tegra: hda: Document interconnect paths Thierry Reding
2020-06-12 14:18 ` [PATCH 17/38] dt-bindings: usb: tegra-xusb: Convert to json-schema Thierry Reding
2020-06-12 14:18 ` [PATCH 18/38] dt-bindings: usb: tegra-xusb: Document interconnect paths Thierry Reding
2020-06-12 14:18 ` [PATCH 19/38] dt-bindings: net: dwc-qos-ethernet: Convert to json-schema Thierry Reding
2020-06-12 14:18 ` [PATCH 20/38] dt-bindings: net: dwc-qos-ethernet: Document interconnect paths Thierry Reding
2020-06-12 14:18 ` [PATCH 21/38] dt-bindings: sound: sgtl5000: Convert to json-schema Thierry Reding
2020-06-18 2:41 ` Rob Herring
2020-06-12 14:18 ` [PATCH 22/38] dt-bindings: gpio: tegra186: Use unique include guard Thierry Reding
2020-06-12 14:18 ` [PATCH 23/38] dt-bindings: gpio: tegra186: Convert to json-schema Thierry Reding
2020-06-18 2:44 ` Rob Herring
2020-06-12 14:18 ` [PATCH 24/38] dt-bindings: mfd: max77620: " Thierry Reding
2020-06-12 14:18 ` [PATCH 25/38] dt-bindings: gpio: tegra: " Thierry Reding
2020-06-17 4:24 ` Dmitry Osipenko
2020-06-17 14:17 ` Thierry Reding
2020-06-17 14:24 ` Dmitry Osipenko
2020-06-17 14:33 ` Dmitry Osipenko
2020-06-17 16:50 ` Thierry Reding
2020-06-18 15:07 ` Dmitry Osipenko
2020-06-12 14:18 ` [PATCH 26/38] dt-bindings: pci: iommu: " Thierry Reding
2020-06-18 2:34 ` Rob Herring
2020-06-18 14:18 ` Thierry Reding
2020-06-19 6:45 ` Thierry Reding
2020-06-12 14:18 ` [PATCH 27/38] dt-bindings: tegra: Add missing compatible strings Thierry Reding
2020-06-12 14:18 ` [PATCH 28/38] dt-bindings: phy: tegra-xusb: Convert to json-schema Thierry Reding
2020-06-18 2:38 ` Rob Herring
2020-06-19 6:47 ` Thierry Reding
2020-06-12 14:18 ` [PATCH 29/38] dt-bindings: tegra: pmc: Increase clock limit for power domains Thierry Reding
2020-06-12 14:18 ` [PATCH 30/38] dt-bindings: panel: Allow reg property for DSI panels Thierry Reding
2020-06-12 14:29 ` Rob Herring
2020-06-16 14:35 ` Thierry Reding
2020-06-12 14:18 ` [PATCH 31/38] dt-bindings: panel: simple: Use unevaluatedProperties Thierry Reding
2020-06-12 14:28 ` Rob Herring
2020-06-16 14:33 ` Thierry Reding
2020-06-12 14:18 ` [PATCH 32/38] dt-bindings: leds: Document rfkill* trigger Thierry Reding
2020-06-12 14:18 ` [PATCH 33/38] dt-bindings: memory-controller: Document Tegra132 EMC Thierry Reding
2020-06-12 14:18 ` [PATCH 34/38] dt-bindings: memory-controller: Fix "reg" entries on Tegra194 Thierry Reding
2020-06-12 14:19 ` [PATCH 35/38] dt-bindings: memory: Update Tegra210 EMC bindings Thierry Reding
2020-06-18 15:36 ` Rob Herring
2020-06-12 14:19 ` [PATCH 36/38] dt-bindings: power: supply: sbs-battery: Document TI BQ20Z45 compatible Thierry Reding
2020-06-12 14:19 ` [PATCH 37/38] dt-bindings: pwm: Explicitly include pwm.yaml Thierry Reding
2020-06-18 2:51 ` Rob Herring
2020-06-19 7:46 ` Thierry Reding
2020-06-19 18:05 ` Rob Herring
2020-06-12 14:19 ` [PATCH 38/38] dt-bindings: serial: Document Tegra-specific properties Thierry Reding
2020-06-18 2:47 ` Rob Herring
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200617225506.GC2975260@bogus \
--to=robh@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).