From: Lars Povlsen <lars.povlsen@microchip.com>
To: Mark Brown <broonie@kernel.org>, SoC Team <soc@kernel.org>,
Rob Herring <robh+dt@kernel.org>
Cc: Lars Povlsen <lars.povlsen@microchip.com>,
Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
<linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Serge Semin <fancer.lancer@gmail.com>,
Serge Semin <Sergey.Semin@baikalelectronics.ru>
Subject: [PATCH v2 4/6] dt-bindings: snps,dw-apb-ssi: Add sparx5, SPI slave snps,rx-sample-delay-ns and microchip,spi-interface2 properties.
Date: Fri, 19 Jun 2020 13:31:19 +0200 [thread overview]
Message-ID: <20200619113121.9984-5-lars.povlsen@microchip.com> (raw)
In-Reply-To: <20200619113121.9984-1-lars.povlsen@microchip.com>
This has the following changes for the snps,dw-apb-ss DT bindings:
- Add "microchip,sparx5-spi" as the compatible for the Sparx5 SoC
controller,
- Add the property "snps,rx-sample-delay-ns" for SPI slaves
- Add the property "microchip,spi-interface2" for SPI slaves
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
.../bindings/spi/snps,dw-apb-ssi.yaml | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index c62cbe79f00dd..5bca4f0493bdf 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -36,6 +36,11 @@ properties:
- mscc,ocelot-spi
- mscc,jaguar2-spi
- const: snps,dw-apb-ssi
+ - description: Microchip Sparx5 SoC SPI Controller
+ items:
+ - enum:
+ - microchip,sparx5-spi
+ - const: snps,dw-apb-ssi
- description: Amazon Alpine SPI Controller
const: amazon,alpine-dw-apb-ssi
- description: Renesas RZ/N1 SPI Controller
@@ -107,6 +112,19 @@ patternProperties:
spi-tx-bus-width:
const: 1
+ snps,rx-sample-delay-ns:
+ description: SPI Rx sample delay offset, unit is nanoseconds.
+ The delay from the default sample time before the actual
+ sample of the rxd input signal occurs. The "rx_sample_delay"
+ is an optional feature of the designware controller, and the
+ upper limit is also subject to controller configuration.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ microchip,spi-interface2:
+ description: indicates the spi device is placed on a special
+ controller interface of the "microchip,sparx5-spi" controller.
+ type: boolean
+
unevaluatedProperties: false
required:
@@ -129,5 +147,11 @@ examples:
num-cs = <2>;
cs-gpios = <&gpio0 13 0>,
<&gpio0 14 0>;
+ spi-flash@1 {
+ compatible = "spi-nand";
+ reg = <1>;
+ microchip,spi-interface2;
+ snps,rx-sample-delay-ns = <7>;
+ };
};
...
--
2.27.0
next prev parent reply other threads:[~2020-06-19 11:31 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-19 11:31 [PATCH v2 0/6] spi: Adding support for Microchip Sparx5 SoC Lars Povlsen
2020-06-19 11:31 ` [PATCH v2 1/6] spi: dw: Add support for RX sample delay register Lars Povlsen
2020-06-19 11:31 ` [PATCH v2 2/6] arm64: dts: sparx5: Add SPI controller Lars Povlsen
2020-06-19 11:31 ` [PATCH v2 3/6] spi: dw: Add Microchip Sparx5 support Lars Povlsen
[not found] ` <20200619121107.GE5396@sirena.org.uk>
2020-06-22 10:46 ` Lars Povlsen
[not found] ` <20200622121706.GF4560@sirena.org.uk>
2020-06-23 13:53 ` Lars Povlsen
2020-06-23 14:08 ` Mark Brown
2020-07-02 10:05 ` Lars Povlsen
2020-06-19 11:31 ` Lars Povlsen [this message]
2020-06-19 11:31 ` [PATCH v2 5/6] arm64: dts: sparx5: Add spi-nor support Lars Povlsen
2020-06-19 11:31 ` [PATCH v2 6/6] arm64: dts: sparx5: Add spi-nand devices Lars Povlsen
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