From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81297C433E1 for ; Fri, 26 Jun 2020 15:42:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5A94E20706 for ; Fri, 26 Jun 2020 15:42:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="oyj/NEPj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727054AbgFZPmz (ORCPT ); Fri, 26 Jun 2020 11:42:55 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:59380 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726361AbgFZPmz (ORCPT ); Fri, 26 Jun 2020 11:42:55 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05QFgejC096131; Fri, 26 Jun 2020 10:42:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1593186160; bh=nvx312mv4VGvwwIjEoy4EfaLo8OvbsRscw5gPQDVBlY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oyj/NEPjKelpOnJyCG7t0Xv9vr3fhklcM10K6XnRfhzmqb7V0IrN3cGEXKqzCS7uI qitjly3MmvGkJJATXnZvNsQXRgNSmEI85On+/wuQ/HEsR50VAwTgrUgTNalOGTkOkk LbjuHYRKrfmPYxUZ9SokGS3ktU/mtRr/GNdufxPY= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05QFgei8080472 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 26 Jun 2020 10:42:40 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 26 Jun 2020 10:42:40 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 26 Jun 2020 10:42:40 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05QFge5p083900; Fri, 26 Jun 2020 10:42:40 -0500 From: Dan Murphy To: , , , CC: , , , , Dan Murphy Subject: [PATCH 2/4] dt-bindings: tas2562: Add voltage sense slot property Date: Fri, 26 Jun 2020 10:41:41 -0500 Message-ID: <20200626154143.20351-2-dmurphy@ti.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200626154143.20351-1-dmurphy@ti.com> References: <20200626154143.20351-1-dmurphy@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a property to configure the slot for the voltage sense monitoring of the device. Vsense data will be sent to the processor via the slot defined by the property Signed-off-by: Dan Murphy --- Documentation/devicetree/bindings/sound/tas2562.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/tas2562.txt b/Documentation/devicetree/bindings/sound/tas2562.txt index fd0ac8636c01..dc6d7362ded7 100644 --- a/Documentation/devicetree/bindings/sound/tas2562.txt +++ b/Documentation/devicetree/bindings/sound/tas2562.txt @@ -11,6 +11,8 @@ Required properties: - compatible: - Should contain "ti,tas2562", "ti,tas2563". - reg: - The i2c address. Should be 0x4c, 0x4d, 0x4e or 0x4f. - ti,imon-slot-no:- TDM TX current sense time slot. + - ti,vmon-slot-no:- TDM TX voltage sense time slot. This slot must always be + greater then ti,imon-slot-no. Optional properties: - interrupt-parent: phandle to the interrupt controller which provides @@ -30,5 +32,6 @@ tas2562@4c { shut-down-gpio = <&gpio1 15 0>; ti,imon-slot-no = <0>; + ti,vmon-slot-no = <1>; }; -- 2.26.2