From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B35C0C433DF for ; Wed, 8 Jul 2020 05:00:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9431E2078C for ; Wed, 8 Jul 2020 05:00:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="S6qB1hgQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728234AbgGHFAT (ORCPT ); Wed, 8 Jul 2020 01:00:19 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:17582 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728542AbgGHFAS (ORCPT ); Wed, 8 Jul 2020 01:00:18 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 07 Jul 2020 22:00:05 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 07 Jul 2020 22:00:17 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 07 Jul 2020 22:00:17 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jul 2020 05:00:13 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 8 Jul 2020 05:00:13 +0000 Received: from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.173.140]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 07 Jul 2020 22:00:13 -0700 From: Krishna Reddy To: , , , , , CC: , , , , , , , , , , , , , , Krishna Reddy Subject: [PATCH v10 1/5] iommu/arm-smmu: move TLB timeout and spin count macros Date: Tue, 7 Jul 2020 22:00:13 -0700 Message-ID: <20200708050017.31563-2-vdumpa@nvidia.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200708050017.31563-1-vdumpa@nvidia.com> References: <20200708050017.31563-1-vdumpa@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594184405; bh=CtbOxBtDQ8YKkBKoHAd6BN8kEl9MRNPz2T4pyCrciLE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=S6qB1hgQ2DEiLBHH/f7WIcQiUQYQRxt91DEFQxDOgvoQNxnTXDcDFQh7pGNGpcMz1 2ei+CqcM4vFcCJXbuMOh6FWrlUWk0ZxPmlP3O6d/Gu45Cny/nJhVQ3nya6okn0ezjw 6UBXi/z5ZI69RT8Jv8hIv6R2sXx6Ycgzhc/JCKjgT+PirijgYHiIWf7W1AMXZbce/Y 1BCV1ZxqDEWRCwyuorr+xc+Qp0n7eZ3+eShXptPsW99c+50n/zhycapM06bytkwPy2 V8fYOA4Stl0xV5xbUBrTn7TbpFb3giNKjr/8vcL/cKv0wbV6U75zYx/RqBtwsh3kYT HZ/bvmiw4D5aw== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Move TLB timeout and spin count macros to header file to allow using the same from vendor specific implementations. Signed-off-by: Krishna Reddy --- drivers/iommu/arm-smmu.c | 3 --- drivers/iommu/arm-smmu.h | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 243bc4cb2705..d2054178df35 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -52,9 +52,6 @@ */ #define QCOM_DUMMY_VAL -1 =20 -#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ -#define TLB_SPIN_COUNT 10 - #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 =20 diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index d172c024be61..c7d0122a7c6c 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -236,6 +236,8 @@ enum arm_smmu_cbar_type { /* Maximum number of context banks per SMMU */ #define ARM_SMMU_MAX_CBS 128 =20 +#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ +#define TLB_SPIN_COUNT 10 =20 /* Shared driver definitions */ enum arm_smmu_arch_version { --=20 2.26.2