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Sun, 12 Jul 2020 09:57:21 -0700 (PDT) Date: Sun, 12 Jul 2020 22:27:15 +0530 From: Manivannan Sadhasivam To: Cristian Ciocaltea Cc: Stephen Boyd , Andreas =?iso-8859-1?Q?F=E4rber?= , Rob Herring , Michael Turquette , Philipp Zabel , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-actions@lists.infradead.org Subject: Re: [PATCH v3 3/6] clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC Message-ID: <20200712165715.GB6110@Mani-XPS-13-9360> References: <87964ae012e513597b8b4c7be2e7ac332a70087a.1593788312.git.cristian.ciocaltea@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87964ae012e513597b8b4c7be2e7ac332a70087a.1593788312.git.cristian.ciocaltea@gmail.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Jul 03, 2020 at 08:05:09PM +0300, Cristian Ciocaltea wrote: > Add support for the missing APB, DMAC and GPIO clocks in the Actions > Semi S500 SoC clock driver. > > Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam Thanks, Mani > --- > Changes in v3: > - None > > Changes in v2: > - None > > drivers/clk/actions/owl-s500.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c > index 0eb83a0b70bc..025a8f6d6482 100644 > --- a/drivers/clk/actions/owl-s500.c > +++ b/drivers/clk/actions/owl-s500.c > @@ -175,6 +175,8 @@ static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RAT > static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT); > > /* gate clocks */ > +static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0); > +static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0); > static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED); > static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED); > static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED); > @@ -184,6 +186,7 @@ static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0); > > /* divider clocks */ > static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0); > +static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); > static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0); > > /* factor clocks */ > @@ -428,6 +431,9 @@ static struct owl_clk_common *s500_clks[] = { > &spdif_clk.common, > &nand_clk.common, > &ecc_clk.common, > + &apb_clk.common, > + &dmac_clk.common, > + &gpio_clk.common, > }; > > static struct clk_hw_onecell_data s500_hw_clks = { > @@ -484,6 +490,9 @@ static struct clk_hw_onecell_data s500_hw_clks = { > [CLK_SPDIF] = &spdif_clk.common.hw, > [CLK_NAND] = &nand_clk.common.hw, > [CLK_ECC] = &ecc_clk.common.hw, > + [CLK_APB] = &apb_clk.common.hw, > + [CLK_DMAC] = &dmac_clk.common.hw, > + [CLK_GPIO] = &gpio_clk.common.hw, > }, > .num = CLK_NR_CLKS, > }; > -- > 2.27.0 >