From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AFA8C433E5 for ; Fri, 17 Jul 2020 16:01:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 78BF820775 for ; Fri, 17 Jul 2020 16:01:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1595001662; bh=PHFcsOvSx0eeMSnfIXvWspi9b5ibhDTxlVNjTZcilaM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=Rm8Rhx4FEad5JwtU9+ejZjsxyoKiOKnfuokCFS0P1y4WJkmbj+LExuS7x2WlBsg6+ f0uq5IhvqxTCdp2sJaBkPPwXenhABRonx6My1BMnMq+YOf4hs9R4RdGYV7qcC0btvP Ukv5WL9LUxHBA04+WAyNKOkvKchB4vkrSmo7Awus= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727010AbgGQQBB (ORCPT ); Fri, 17 Jul 2020 12:01:01 -0400 Received: from mail.kernel.org ([198.145.29.99]:40822 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727002AbgGQQBB (ORCPT ); Fri, 17 Jul 2020 12:01:01 -0400 Received: from wens.tw (mirror2.csie.ntu.edu.tw [140.112.194.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 54E2F21741; Fri, 17 Jul 2020 16:01:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1595001660; bh=PHFcsOvSx0eeMSnfIXvWspi9b5ibhDTxlVNjTZcilaM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FI+KBFNJvoZrc2MqqB1ASo9dbFdqGwL70n/9fpNpVIeU/t2Fv+bAzy7vaEdocmFPp m5+vAj0SFdMDFc8spft59hG81cUJVM10pta6YG/I8ZbFFVLroqCFqEbtgzQuySKCsy rAzxGtKt60uhm16kPNCq1xUMTnrKRqdt4cSpZfa0= Received: by wens.tw (Postfix, from userid 1000) id 45C965FDC0; Sat, 18 Jul 2020 00:00:55 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard Cc: Chen-Yu Tsai , Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/8] arm64: dts: allwinner: h5: Add CPU Operating Performance Points table Date: Sat, 18 Jul 2020 00:00:51 +0800 Message-Id: <20200717160053.31191-7-wens@kernel.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200717160053.31191-1-wens@kernel.org> References: <20200717160053.31191-1-wens@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Chen-Yu Tsai Add an OPP (Operating Performance Points) table for the CPU cores for boards to include to DVFS (Dynamic Voltage & Frequency Scaling) on the H5. The table originates from Armbian, but the maximum voltage is raised slightly to account for boards using slightly higher voltages. The table and tie in to the CPU cores are put in a separate dtsi file that board files can include to opt in. Or they can define their own tables if the standard one does not fit. This has been tested on the Libre Computer ALL-H3-CC-H5 and the Bananapi M2+ v1.2 H5, both with adequate cooling. The former has a fixed 1.2V regulator, while the latter has a GPIO controlled regulator switchable between 1.1V and 1.3V. Signed-off-by: Chen-Yu Tsai --- Unfortunately I couldn't find the original source and author for the OPP table. So for now I put my name on it. If someone wants to claim authorship please do so. --- .../boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi new file mode 100644 index 000000000000..9d3a9fa78e2e --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Chen-Yu Tsai + +/ { + cpu_opp_table: opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <1000000 1000000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@648000000 { + opp-hz = /bits/ 64 <648000000>; + opp-microvolt = <1040000 1040000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1080000 1080000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <1120000 1120000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-microvolt = <1160000 1160000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1200000 1200000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1240000 1240000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1260000 1260000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp@1152000000 { + opp-hz = /bits/ 64 <1152000000>; + opp-microvolt = <1300000 1300000 1310000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opp_table>; +}; -- 2.27.0