Re: [PATCH 19/20] media: rcar-vin: Enable support for R8A774E1

Niklas
2020-07-17T13:19:09Z

Hi Lad,

Thanks for your work.

On 2020-07-16 18:18:34 +0100, Lad Prabhakar wrote:
> Add the SoC specific information for RZ/G2H (R8A774E1) SoC. Also add
> the routing information between CSI2 and VIN (which is similar to
> R-Car H3 except it lacks CSI41).
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>

I do not have access to the datasheet so I can't verify the routing
table so I trust it is correct.

Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

> ---
> drivers/media/platform/rcar-vin/rcar-core.c | 40 +++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
> index 7440c8965d27..4fb76d1df308 100644
> --- a/drivers/media/platform/rcar-vin/rcar-core.c
> +++ b/drivers/media/platform/rcar-vin/rcar-core.c
> @@ -944,6 +944,42 @@ static const struct rvin_info rcar_info_gen2 = {
> .max_height = 2048,
> };
>
> +static const struct rvin_group_route rcar_info_r8a774e1_routes[] = {
> + { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) },
> + { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) },
> + { .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) },
> + { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) },
> + { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) },
> + { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) },
> + { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) },
> + { .csi = RVIN_CSI20, .channel = 1, .vin = 2, .mask = BIT(0) },
> + { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) },
> + { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) },
> + { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) },
> + { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) },
> + { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) },
> + { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) | BIT(2) },
> + { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) },
> + { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) },
> + { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) },
> + { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) },
> + { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) },
> + { .csi = RVIN_CSI20, .channel = 1, .vin = 6, .mask = BIT(0) },
> + { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) },
> + { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) },
> + { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) | BIT(2) },
> + { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) },
> + { /* Sentinel */ }
> +};
> +
> +static const struct rvin_info rcar_info_r8a774e1 = {
> + .model = RCAR_GEN3,
> + .use_mc = true,
> + .max_width = 4096,
> + .max_height = 4096,
> + .routes = rcar_info_r8a774e1_routes,
> +};
> +
> static const struct rvin_group_route rcar_info_r8a7795_routes[] = {
> { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) },
> { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) },
> @@ -1220,6 +1256,10 @@ static const struct of_device_id rvin_of_id_table[] = {
> .compatible = "renesas,vin-r8a774c0",
> .data = &rcar_info_r8a77990,
> },
> + {
> + .compatible = "renesas,vin-r8a774e1",
> + .data = &rcar_info_r8a774e1,
> + },
> {
> .compatible = "renesas,vin-r8a7778",
> .data = &rcar_info_m1,
> --
> 2.17.1
>

--
Regards,
Niklas Söderlund