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Thu, 23 Jul 2020 09:59:51 -0700 (PDT) Received: from xps15 ([64.188.179.252]) by smtp.gmail.com with ESMTPSA id 5sm1721954ion.7.2020.07.23.09.59.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2020 09:59:51 -0700 (PDT) Received: (nullmailer pid 531537 invoked by uid 1000); Thu, 23 Jul 2020 16:59:50 -0000 Date: Thu, 23 Jul 2020 10:59:50 -0600 From: Rob Herring To: Yongqiang Niu Cc: CK Hu , Philipp Zabel , Matthias Brugger , David Airlie , Daniel Vetter , Mark Rutland , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: Re: [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display Message-ID: <20200723165950.GA529262@bogus> References: <1595469798-3824-1-git-send-email-yongqiang.niu@mediatek.com> <1595469798-3824-5-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1595469798-3824-5-git-send-email-yongqiang.niu@mediatek.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Jul 23, 2020 at 10:03:15AM +0800, Yongqiang Niu wrote: > Update device tree binding document for rdma_fifo_size > > Signed-off-by: Yongqiang Niu > --- > .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > index b91e709..e6bbe32 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > @@ -66,6 +66,11 @@ Required properties (DMA function blocks): > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > for details. > > +Optional properties (RDMA function blocks): > +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC, add this s/_/-/ > + property to the corresponding rdma > + the value is the Max value which defined in hardware data sheet. > + > Examples: > > mmsys: clock-controller@14000000 { > @@ -207,3 +212,12 @@ od@14023000 { > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; > clocks = <&mmsys CLK_MM_DISP_OD>; > }; > + > +rdma1: rdma@1400c000 { > + compatible = "mediatek,mt8183-disp-rdma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = ; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + mediatek,rdma_fifo_size = <2048>; > +}; > -- > 1.8.1.1.dirty