From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B1B1C433DF for ; Wed, 12 Aug 2020 14:13:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D0A2120855 for ; Wed, 12 Aug 2020 14:13:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726696AbgHLONS (ORCPT ); Wed, 12 Aug 2020 10:13:18 -0400 Received: from relay1-d.mail.gandi.net ([217.70.183.193]:63699 "EHLO relay1-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726681AbgHLONR (ORCPT ); Wed, 12 Aug 2020 10:13:17 -0400 X-Originating-IP: 91.224.148.103 Received: from localhost.localdomain (unknown [91.224.148.103]) (Authenticated sender: miquel.raynal@bootlin.com) by relay1-d.mail.gandi.net (Postfix) with ESMTPSA id AEFA1240009; Wed, 12 Aug 2020 14:13:14 +0000 (UTC) From: Miquel Raynal To: Boris Brezillon , linux-i3c@lists.infradead.org, Rob Herring , Cc: Nicolas Pitre , Rajeev Huralikoppi , Conor Culhane , , Thomas Petazzoni , Miquel Raynal Subject: [PATCH v2 2/4] dt-bindings: i3c: Describe Silvaco master binding Date: Wed, 12 Aug 2020 16:13:10 +0200 Message-Id: <20200812141312.3331-2-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200812141312.3331-1-miquel.raynal@bootlin.com> References: <20200812141312.3331-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Silvaco provide a dual-role I3C master. Description is rather simple: it needs a register mapping, three clocks and an interrupt. Signed-off-by: Miquel Raynal --- Changes in v2: * Updated Rob's tool and fixed the mistake reported. * Updated the vendor prefix. .../bindings/i3c/silvaco,i3c-master.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml diff --git a/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml new file mode 100644 index 000000000000..63731e8a9068 --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/silvaco,i3c-master.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i3c/silvaco,i3c-master.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silvaco I3C master + +maintainers: + - Conor Culhane + +properties: + compatible: + const: silvaco,i3c-master + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + description: | + There are three clocks: + pclk: System clock + fast_clk: Fast clock (for the bus) + slow_clk: Slow clock (for other events) + + items: + - const: pclk + - const: fast_clk + - const: slow_clk + + clocks: + minItems: 3 + maxItems: 3 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + +examples: + - | + i3c-master@a0000000 { + compatible = "silvaco,i3c-master"; + clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>; + clock-names = "pclk", "fast_clk", "slow_clk"; + interrupt-parent = <&gic>; + interrupts = <0 89 4>; + reg = <0xa0000000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; -- 2.20.1