[PATCH v2 1/2] dt-bindings: phy-imx8mq-usb: add compatible string for imx8mp usb phy

[PATCH v2 1/2] dt-bindings: phy-imx8mq-usb: add compatible string for imx8mp usb phy

[Li Jun]

Add "fsl,imx8mp-usb-phy" compatible string for imx8mp usb phy, which is
similar with imx8mq usb phy but with some different customizations.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Li Jun <jun.li@nxp.com>
---
no changes.

 Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt
index ed47e5c..7c70f2a 100644
--- a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt
@@ -1,7 +1,7 @@
 * Freescale i.MX8MQ USB3 PHY binding
 
 Required properties:
-- compatible:	Should be "fsl,imx8mq-usb-phy"
+- compatible:	Should be "fsl,imx8mq-usb-phy" or "fsl,imx8mp-usb-phy"
 - #phys-cells:	must be 0 (see phy-bindings.txt in this directory)
 - reg:		The base address and length of the registers
 - clocks:	phandles to the clocks for each clock listed in clock-names
-- 
2.7.4

[PATCH v2 2/2] phy: freescale: imx8mq-usb: add support for imx8mp usb phy

[Li Jun]

Add initial support for imx8mp usb phy support, imx8mp usb has
a silimar phy as imx8mq, which has some different customizations
on clock and low power design when SoC integration.

Signed-off-by: Li Jun <jun.li@nxp.com>
---
Changes for v2:
- Add header files in alphabetical order.
- Use FIELD_PREP to get the target value to set.
- Use of_device_get_match_data() to get match data for phy ops.
  
 drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 76 +++++++++++++++++++++++++++---
 1 file changed, 69 insertions(+), 7 deletions(-)

diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
index 0c4833d..abd3151 100644
--- a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
+++ b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
@@ -2,14 +2,18 @@
 /* Copyright (c) 2017 NXP. */
 
 #include <linux/clk.h>
+#include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/of_platform.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/regulator/consumer.h>
 
 #define PHY_CTRL0			0x0
 #define PHY_CTRL0_REF_SSP_EN		BIT(2)
+#define PHY_CTRL0_FSEL_MASK		GENMASK(10, 5)
+#define PHY_CTRL0_FSEL_24M		0x2a
 
 #define PHY_CTRL1			0x4
 #define PHY_CTRL1_RESET			BIT(0)
@@ -20,6 +24,11 @@
 
 #define PHY_CTRL2			0x8
 #define PHY_CTRL2_TXENABLEN0		BIT(8)
+#define PHY_CTRL2_OTG_DISABLE		BIT(9)
+
+#define PHY_CTRL6			0x18
+#define PHY_CTRL6_ALT_CLK_EN		BIT(1)
+#define PHY_CTRL6_ALT_CLK_SEL		BIT(0)
 
 struct imx8mq_usb_phy {
 	struct phy *phy;
@@ -54,6 +63,44 @@ static int imx8mq_usb_phy_init(struct phy *phy)
 	return 0;
 }
 
+static int imx8mp_usb_phy_init(struct phy *phy)
+{
+	struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
+	u32 value;
+
+	/* USB3.0 PHY signal fsel for 24M ref */
+	value = readl(imx_phy->base + PHY_CTRL0);
+	value &= ~PHY_CTRL0_FSEL_MASK;
+	value |= FIELD_PREP(PHY_CTRL0_FSEL_MASK, PHY_CTRL0_FSEL_24M);
+	writel(value, imx_phy->base + PHY_CTRL0);
+
+	/* Disable alt_clk_en and use internal MPLL clocks */
+	value = readl(imx_phy->base + PHY_CTRL6);
+	value &= ~(PHY_CTRL6_ALT_CLK_SEL | PHY_CTRL6_ALT_CLK_EN);
+	writel(value, imx_phy->base + PHY_CTRL6);
+
+	value = readl(imx_phy->base + PHY_CTRL1);
+	value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0);
+	value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
+	writel(value, imx_phy->base + PHY_CTRL1);
+
+	value = readl(imx_phy->base + PHY_CTRL0);
+	value |= PHY_CTRL0_REF_SSP_EN;
+	writel(value, imx_phy->base + PHY_CTRL0);
+
+	value = readl(imx_phy->base + PHY_CTRL2);
+	value |= PHY_CTRL2_TXENABLEN0 | PHY_CTRL2_OTG_DISABLE;
+	writel(value, imx_phy->base + PHY_CTRL2);
+
+	udelay(10);
+
+	value = readl(imx_phy->base + PHY_CTRL1);
+	value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
+	writel(value, imx_phy->base + PHY_CTRL1);
+
+	return 0;
+}
+
 static int imx8mq_phy_power_on(struct phy *phy)
 {
 	struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
@@ -83,12 +130,29 @@ static struct phy_ops imx8mq_usb_phy_ops = {
 	.owner		= THIS_MODULE,
 };
 
+static struct phy_ops imx8mp_usb_phy_ops = {
+	.init		= imx8mp_usb_phy_init,
+	.power_on	= imx8mq_phy_power_on,
+	.power_off	= imx8mq_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static const struct of_device_id imx8mq_usb_phy_of_match[] = {
+	{.compatible = "fsl,imx8mq-usb-phy",
+	 .data = &imx8mq_usb_phy_ops,},
+	{.compatible = "fsl,imx8mp-usb-phy",
+	 .data = &imx8mp_usb_phy_ops,},
+	{ }
+};
+MODULE_DEVICE_TABLE(of, imx8mq_usb_phy_of_match);
+
 static int imx8mq_usb_phy_probe(struct platform_device *pdev)
 {
 	struct phy_provider *phy_provider;
 	struct device *dev = &pdev->dev;
 	struct imx8mq_usb_phy *imx_phy;
 	struct resource *res;
+	const struct phy_ops *phy_ops;
 
 	imx_phy = devm_kzalloc(dev, sizeof(*imx_phy), GFP_KERNEL);
 	if (!imx_phy)
@@ -105,7 +169,11 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev)
 	if (IS_ERR(imx_phy->base))
 		return PTR_ERR(imx_phy->base);
 
-	imx_phy->phy = devm_phy_create(dev, NULL, &imx8mq_usb_phy_ops);
+	phy_ops = of_device_get_match_data(dev);
+	if (!phy_ops)
+		return -EINVAL;
+
+	imx_phy->phy = devm_phy_create(dev, NULL, phy_ops);
 	if (IS_ERR(imx_phy->phy))
 		return PTR_ERR(imx_phy->phy);
 
@@ -120,12 +188,6 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev)
 	return PTR_ERR_OR_ZERO(phy_provider);
 }
 
-static const struct of_device_id imx8mq_usb_phy_of_match[] = {
-	{.compatible = "fsl,imx8mq-usb-phy",},
-	{ },
-};
-MODULE_DEVICE_TABLE(of, imx8mq_usb_phy_of_match);
-
 static struct platform_driver imx8mq_usb_phy_driver = {
 	.probe	= imx8mq_usb_phy_probe,
 	.driver = {
-- 
2.7.4

Re: [PATCH v2 2/2] phy: freescale: imx8mq-usb: add support for imx8mp usb phy

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 3517 bytes --]

Hi Li,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v5.9-rc2 next-20200824]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Li-Jun/dt-bindings-phy-imx8mq-usb-add-compatible-string-for-imx8mp-usb-phy/20200824-144136
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm-randconfig-r024-20200824 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project b587ca93be114d07ec3bf654add97d7872325281)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm cross compiling tool for clang build
        # apt-get install binutils-arm-linux-gnueabi
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/phy/freescale/phy-fsl-imx8mq-usb.c:74:11: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
           value |= FIELD_PREP(PHY_CTRL0_FSEL_MASK, PHY_CTRL0_FSEL_24M);
                    ^
   1 error generated.

# https://github.com/0day-ci/linux/commit/e9388d5c8e328a7be2ffe214e8c6a5d510eecf1c
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Li-Jun/dt-bindings-phy-imx8mq-usb-add-compatible-string-for-imx8mp-usb-phy/20200824-144136
git checkout e9388d5c8e328a7be2ffe214e8c6a5d510eecf1c
vim +/FIELD_PREP +74 drivers/phy/freescale/phy-fsl-imx8mq-usb.c

    65	
    66	static int imx8mp_usb_phy_init(struct phy *phy)
    67	{
    68		struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
    69		u32 value;
    70	
    71		/* USB3.0 PHY signal fsel for 24M ref */
    72		value = readl(imx_phy->base + PHY_CTRL0);
    73		value &= ~PHY_CTRL0_FSEL_MASK;
  > 74		value |= FIELD_PREP(PHY_CTRL0_FSEL_MASK, PHY_CTRL0_FSEL_24M);
    75		writel(value, imx_phy->base + PHY_CTRL0);
    76	
    77		/* Disable alt_clk_en and use internal MPLL clocks */
    78		value = readl(imx_phy->base + PHY_CTRL6);
    79		value &= ~(PHY_CTRL6_ALT_CLK_SEL | PHY_CTRL6_ALT_CLK_EN);
    80		writel(value, imx_phy->base + PHY_CTRL6);
    81	
    82		value = readl(imx_phy->base + PHY_CTRL1);
    83		value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0);
    84		value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
    85		writel(value, imx_phy->base + PHY_CTRL1);
    86	
    87		value = readl(imx_phy->base + PHY_CTRL0);
    88		value |= PHY_CTRL0_REF_SSP_EN;
    89		writel(value, imx_phy->base + PHY_CTRL0);
    90	
    91		value = readl(imx_phy->base + PHY_CTRL2);
    92		value |= PHY_CTRL2_TXENABLEN0 | PHY_CTRL2_OTG_DISABLE;
    93		writel(value, imx_phy->base + PHY_CTRL2);
    94	
    95		udelay(10);
    96	
    97		value = readl(imx_phy->base + PHY_CTRL1);
    98		value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
    99		writel(value, imx_phy->base + PHY_CTRL1);
   100	
   101		return 0;
   102	}
   103	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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Re: [PATCH v2 2/2] phy: freescale: imx8mq-usb: add support for imx8mp usb phy

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 3464 bytes --]

Hi Li,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master phy/next v5.9-rc2 next-20200824]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Li-Jun/dt-bindings-phy-imx8mq-usb-add-compatible-string-for-imx8mp-usb-phy/20200824-144136
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: nios2-randconfig-r005-20200824 (attached as .config)
compiler: nios2-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=nios2 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/phy/freescale/phy-fsl-imx8mq-usb.c: In function 'imx8mp_usb_phy_init':
>> drivers/phy/freescale/phy-fsl-imx8mq-usb.c:74:11: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
      74 |  value |= FIELD_PREP(PHY_CTRL0_FSEL_MASK, PHY_CTRL0_FSEL_24M);
         |           ^~~~~~~~~~
   cc1: some warnings being treated as errors

# https://github.com/0day-ci/linux/commit/e9388d5c8e328a7be2ffe214e8c6a5d510eecf1c
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Li-Jun/dt-bindings-phy-imx8mq-usb-add-compatible-string-for-imx8mp-usb-phy/20200824-144136
git checkout e9388d5c8e328a7be2ffe214e8c6a5d510eecf1c
vim +/FIELD_PREP +74 drivers/phy/freescale/phy-fsl-imx8mq-usb.c

    65	
    66	static int imx8mp_usb_phy_init(struct phy *phy)
    67	{
    68		struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
    69		u32 value;
    70	
    71		/* USB3.0 PHY signal fsel for 24M ref */
    72		value = readl(imx_phy->base + PHY_CTRL0);
    73		value &= ~PHY_CTRL0_FSEL_MASK;
  > 74		value |= FIELD_PREP(PHY_CTRL0_FSEL_MASK, PHY_CTRL0_FSEL_24M);
    75		writel(value, imx_phy->base + PHY_CTRL0);
    76	
    77		/* Disable alt_clk_en and use internal MPLL clocks */
    78		value = readl(imx_phy->base + PHY_CTRL6);
    79		value &= ~(PHY_CTRL6_ALT_CLK_SEL | PHY_CTRL6_ALT_CLK_EN);
    80		writel(value, imx_phy->base + PHY_CTRL6);
    81	
    82		value = readl(imx_phy->base + PHY_CTRL1);
    83		value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0);
    84		value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
    85		writel(value, imx_phy->base + PHY_CTRL1);
    86	
    87		value = readl(imx_phy->base + PHY_CTRL0);
    88		value |= PHY_CTRL0_REF_SSP_EN;
    89		writel(value, imx_phy->base + PHY_CTRL0);
    90	
    91		value = readl(imx_phy->base + PHY_CTRL2);
    92		value |= PHY_CTRL2_TXENABLEN0 | PHY_CTRL2_OTG_DISABLE;
    93		writel(value, imx_phy->base + PHY_CTRL2);
    94	
    95		udelay(10);
    96	
    97		value = readl(imx_phy->base + PHY_CTRL1);
    98		value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
    99		writel(value, imx_phy->base + PHY_CTRL1);
   100	
   101		return 0;
   102	}
   103	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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