* [PATCH 1/2] bindings: serial: Add xilinx compatible @ 2020-08-19 16:43 Shubhrajyoti Datta 2020-08-19 16:43 ` [PATCH 2/2] tty: pl011: Add support for xilinx uart Shubhrajyoti Datta 2020-08-25 22:12 ` [PATCH 1/2] bindings: serial: Add xilinx compatible Rob Herring 0 siblings, 2 replies; 5+ messages in thread From: Shubhrajyoti Datta @ 2020-08-19 16:43 UTC (permalink / raw) To: linux-serial Cc: devicetree, jslaby, robh+dt, git-dev, gregkh, Shubhrajyoti Datta Add the arm,xlnx-sbsa-uart compatible. Xilinx versal uart is similar to sbsa-uart except that it has termios configurable. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> --- Documentation/devicetree/bindings/serial/pl011.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml index c23c93b..6e123b1 100644 --- a/Documentation/devicetree/bindings/serial/pl011.yaml +++ b/Documentation/devicetree/bindings/serial/pl011.yaml @@ -20,6 +20,7 @@ select: enum: - arm,pl011 - zte,zx296702-uart + - arm,xlnx-sbsa-uart required: - compatible @@ -32,6 +33,7 @@ properties: - items: - const: zte,zx296702-uart - const: arm,primecell + - const: arm,xlnx-sbsa-uart reg: maxItems: 1 -- 2.7.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] tty: pl011: Add support for xilinx uart 2020-08-19 16:43 [PATCH 1/2] bindings: serial: Add xilinx compatible Shubhrajyoti Datta @ 2020-08-19 16:43 ` Shubhrajyoti Datta 2020-08-25 22:17 ` Rob Herring 2020-08-25 22:12 ` [PATCH 1/2] bindings: serial: Add xilinx compatible Rob Herring 1 sibling, 1 reply; 5+ messages in thread From: Shubhrajyoti Datta @ 2020-08-19 16:43 UTC (permalink / raw) To: linux-serial Cc: devicetree, jslaby, robh+dt, git-dev, gregkh, Shubhrajyoti Datta Xilinx uart is similar to sbsa but it has configurable parity and hardware flow. Add a compatible for the same. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> --- drivers/tty/serial/amba-pl011.c | 77 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 76 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 8efd7c2..41dbcee 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -2073,6 +2073,55 @@ sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, spin_unlock_irqrestore(&port->lock, flags); } +static void +xlnx_sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, + struct ktermios *old) +{ + struct uart_amba_port *uap = + container_of(port, struct uart_amba_port, port); + unsigned long flags; + unsigned int lcr_h, old_cr; + + tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); + /* The SBSA UART only supports 8n1 without hardware flow control. */ + termios->c_cflag &= ~(CMSPAR | CRTSCTS); + switch (termios->c_cflag & CSIZE) { + case CS5: + lcr_h = UART01x_LCRH_WLEN_5; + break; + case CS6: + lcr_h = UART01x_LCRH_WLEN_6; + break; + case CS7: + lcr_h = UART01x_LCRH_WLEN_7; + break; + default: + lcr_h = UART01x_LCRH_WLEN_8; + break; + } + if (termios->c_cflag & CSTOPB) + lcr_h |= UART01x_LCRH_STP2; + if (termios->c_cflag & PARENB) { + lcr_h |= UART01x_LCRH_PEN; + if (!(termios->c_cflag & PARODD)) + lcr_h |= UART01x_LCRH_EPS; + if (termios->c_cflag & CMSPAR) + lcr_h |= UART011_LCRH_SPS; + } + if (uap->fifosize > 1) + lcr_h |= UART01x_LCRH_FEN; + + spin_lock_irqsave(&port->lock, flags); + uart_update_timeout(port, CS8, uap->fixed_baud); + pl011_setup_status_masks(port, termios); + /* first, disable everything */ + old_cr = pl011_read(uap, REG_CR); + pl011_write(0, uap, REG_CR); + pl011_write_lcr_h(uap, lcr_h); + pl011_write(old_cr, uap, REG_CR); + spin_unlock_irqrestore(&port->lock, flags); +} + static const char *pl011_type(struct uart_port *port) { struct uart_amba_port *uap = @@ -2179,6 +2228,28 @@ static const struct uart_ops sbsa_uart_pops = { #endif }; +static const struct uart_ops xlnx_sbsa_uart_pops = { + .tx_empty = pl011_tx_empty, + .set_mctrl = sbsa_uart_set_mctrl, + .get_mctrl = sbsa_uart_get_mctrl, + .stop_tx = pl011_stop_tx, + .start_tx = pl011_start_tx, + .stop_rx = pl011_stop_rx, + .startup = sbsa_uart_startup, + .shutdown = sbsa_uart_shutdown, + .set_termios = xlnx_sbsa_uart_set_termios, + .type = pl011_type, + .release_port = pl011_release_port, + .request_port = pl011_request_port, + .config_port = pl011_config_port, + .verify_port = pl011_verify_port, +#ifdef CONFIG_CONSOLE_POLL + .poll_init = pl011_hwinit, + .poll_get_char = pl011_get_poll_char, + .poll_put_char = pl011_put_poll_char, +#endif +}; + static struct uart_amba_port *amba_ports[UART_NR]; #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE @@ -2754,7 +2825,10 @@ static int sbsa_uart_probe(struct platform_device *pdev) uap->reg_offset = uap->vendor->reg_offset; uap->fifosize = 32; uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; - uap->port.ops = &sbsa_uart_pops; + if (of_device_is_compatible(pdev->dev.of_node, "arm,xlnx-sbsa-uart")) + uap->port.ops = &xlnx_sbsa_uart_pops; + else + uap->port.ops = &sbsa_uart_pops; uap->fixed_baud = baudrate; snprintf(uap->type, sizeof(uap->type), "SBSA"); @@ -2781,6 +2855,7 @@ static int sbsa_uart_remove(struct platform_device *pdev) static const struct of_device_id sbsa_uart_of_match[] = { { .compatible = "arm,sbsa-uart", }, + { .compatible = "arm,xlnx-sbsa-uart", }, {}, }; MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); -- 2.7.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] tty: pl011: Add support for xilinx uart 2020-08-19 16:43 ` [PATCH 2/2] tty: pl011: Add support for xilinx uart Shubhrajyoti Datta @ 2020-08-25 22:17 ` Rob Herring 0 siblings, 0 replies; 5+ messages in thread From: Rob Herring @ 2020-08-25 22:17 UTC (permalink / raw) To: Shubhrajyoti Datta; +Cc: linux-serial, devicetree, jslaby, git-dev, gregkh On Wed, Aug 19, 2020 at 10:13:59PM +0530, Shubhrajyoti Datta wrote: > Xilinx uart is similar to sbsa but it has configurable > parity and hardware flow. Add a compatible for the same. > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > --- > drivers/tty/serial/amba-pl011.c | 77 ++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 76 insertions(+), 1 deletion(-) > > diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c > index 8efd7c2..41dbcee 100644 > --- a/drivers/tty/serial/amba-pl011.c > +++ b/drivers/tty/serial/amba-pl011.c > @@ -2073,6 +2073,55 @@ sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, > spin_unlock_irqrestore(&port->lock, flags); > } > > +static void > +xlnx_sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, > + struct ktermios *old) > +{ > + struct uart_amba_port *uap = > + container_of(port, struct uart_amba_port, port); > + unsigned long flags; > + unsigned int lcr_h, old_cr; > + > + tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); > + /* The SBSA UART only supports 8n1 without hardware flow control. */ > + termios->c_cflag &= ~(CMSPAR | CRTSCTS); > + switch (termios->c_cflag & CSIZE) { > + case CS5: > + lcr_h = UART01x_LCRH_WLEN_5; > + break; > + case CS6: > + lcr_h = UART01x_LCRH_WLEN_6; > + break; > + case CS7: > + lcr_h = UART01x_LCRH_WLEN_7; > + break; > + default: > + lcr_h = UART01x_LCRH_WLEN_8; > + break; > + } > + if (termios->c_cflag & CSTOPB) > + lcr_h |= UART01x_LCRH_STP2; > + if (termios->c_cflag & PARENB) { > + lcr_h |= UART01x_LCRH_PEN; > + if (!(termios->c_cflag & PARODD)) > + lcr_h |= UART01x_LCRH_EPS; > + if (termios->c_cflag & CMSPAR) > + lcr_h |= UART011_LCRH_SPS; > + } > + if (uap->fifosize > 1) > + lcr_h |= UART01x_LCRH_FEN; I'm guessing at least some of the above code is just copy-n-paste from the pl011 version? Can't you reuse the existing version? > + spin_lock_irqsave(&port->lock, flags); > + uart_update_timeout(port, CS8, uap->fixed_baud); > + pl011_setup_status_masks(port, termios); > + /* first, disable everything */ > + old_cr = pl011_read(uap, REG_CR); > + pl011_write(0, uap, REG_CR); > + pl011_write_lcr_h(uap, lcr_h); > + pl011_write(old_cr, uap, REG_CR); > + spin_unlock_irqrestore(&port->lock, flags); > +} > + > static const char *pl011_type(struct uart_port *port) > { > struct uart_amba_port *uap = > @@ -2179,6 +2228,28 @@ static const struct uart_ops sbsa_uart_pops = { > #endif > }; > > +static const struct uart_ops xlnx_sbsa_uart_pops = { > + .tx_empty = pl011_tx_empty, > + .set_mctrl = sbsa_uart_set_mctrl, > + .get_mctrl = sbsa_uart_get_mctrl, > + .stop_tx = pl011_stop_tx, > + .start_tx = pl011_start_tx, > + .stop_rx = pl011_stop_rx, > + .startup = sbsa_uart_startup, > + .shutdown = sbsa_uart_shutdown, > + .set_termios = xlnx_sbsa_uart_set_termios, > + .type = pl011_type, > + .release_port = pl011_release_port, > + .request_port = pl011_request_port, > + .config_port = pl011_config_port, > + .verify_port = pl011_verify_port, > +#ifdef CONFIG_CONSOLE_POLL > + .poll_init = pl011_hwinit, > + .poll_get_char = pl011_get_poll_char, > + .poll_put_char = pl011_put_poll_char, > +#endif > +}; > + > static struct uart_amba_port *amba_ports[UART_NR]; > > #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE > @@ -2754,7 +2825,10 @@ static int sbsa_uart_probe(struct platform_device *pdev) > uap->reg_offset = uap->vendor->reg_offset; > uap->fifosize = 32; > uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; > - uap->port.ops = &sbsa_uart_pops; > + if (of_device_is_compatible(pdev->dev.of_node, "arm,xlnx-sbsa-uart")) > + uap->port.ops = &xlnx_sbsa_uart_pops; > + else > + uap->port.ops = &sbsa_uart_pops; > uap->fixed_baud = baudrate; > > snprintf(uap->type, sizeof(uap->type), "SBSA"); > @@ -2781,6 +2855,7 @@ static int sbsa_uart_remove(struct platform_device *pdev) > > static const struct of_device_id sbsa_uart_of_match[] = { > { .compatible = "arm,sbsa-uart", }, > + { .compatible = "arm,xlnx-sbsa-uart", }, > {}, > }; > MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] bindings: serial: Add xilinx compatible 2020-08-19 16:43 [PATCH 1/2] bindings: serial: Add xilinx compatible Shubhrajyoti Datta 2020-08-19 16:43 ` [PATCH 2/2] tty: pl011: Add support for xilinx uart Shubhrajyoti Datta @ 2020-08-25 22:12 ` Rob Herring 1 sibling, 0 replies; 5+ messages in thread From: Rob Herring @ 2020-08-25 22:12 UTC (permalink / raw) To: Shubhrajyoti Datta; +Cc: linux-serial, devicetree, jslaby, git-dev, gregkh On Wed, Aug 19, 2020 at 10:13:58PM +0530, Shubhrajyoti Datta wrote: > Add the arm,xlnx-sbsa-uart compatible. > Xilinx versal uart is similar to sbsa-uart except that it has > termios configurable. Yet still not just a pl011? Sigh. > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > --- > Documentation/devicetree/bindings/serial/pl011.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml > index c23c93b..6e123b1 100644 > --- a/Documentation/devicetree/bindings/serial/pl011.yaml > +++ b/Documentation/devicetree/bindings/serial/pl011.yaml > @@ -20,6 +20,7 @@ select: > enum: > - arm,pl011 > - zte,zx296702-uart > + - arm,xlnx-sbsa-uart > required: > - compatible > > @@ -32,6 +33,7 @@ properties: > - items: > - const: zte,zx296702-uart > - const: arm,primecell > + - const: arm,xlnx-sbsa-uart You are defining compatible must be: compatible = "zte,zx296702-uart", "arm,primecell", "arm,xlnx-sbsa-uart"; Probably not what you want. And breaks ZTE. ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] bindings: serial: Add xilinx compatible @ 2020-08-19 16:42 Shubhrajyoti Datta 0 siblings, 0 replies; 5+ messages in thread From: Shubhrajyoti Datta @ 2020-08-19 16:42 UTC (permalink / raw) To: linux-serial; +Cc: devicetree, jslaby, robh+dt, gregkh, Shubhrajyoti Datta Add the arm,xlnx-sbsa-uart compatible. Xilinx versal uart is similar to sbsa-uart except that it has termios configurable. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> --- Documentation/devicetree/bindings/serial/pl011.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml index c23c93b..6e123b1 100644 --- a/Documentation/devicetree/bindings/serial/pl011.yaml +++ b/Documentation/devicetree/bindings/serial/pl011.yaml @@ -20,6 +20,7 @@ select: enum: - arm,pl011 - zte,zx296702-uart + - arm,xlnx-sbsa-uart required: - compatible @@ -32,6 +33,7 @@ properties: - items: - const: zte,zx296702-uart - const: arm,primecell + - const: arm,xlnx-sbsa-uart reg: maxItems: 1 -- 2.7.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-08-25 22:17 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-08-19 16:43 [PATCH 1/2] bindings: serial: Add xilinx compatible Shubhrajyoti Datta 2020-08-19 16:43 ` [PATCH 2/2] tty: pl011: Add support for xilinx uart Shubhrajyoti Datta 2020-08-25 22:17 ` Rob Herring 2020-08-25 22:12 ` [PATCH 1/2] bindings: serial: Add xilinx compatible Rob Herring -- strict thread matches above, loose matches on Subject: below -- 2020-08-19 16:42 Shubhrajyoti Datta
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