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Thu, 3 Sep 2020 10:15:15 +0000 From: fugang.duan@nxp.com To: shawnguo@kernel.org, robh+dt@kernel.org, gregkh@linuxfoundation.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, festevam@gmail.com, kernel@pengutronix.de, s.hauer@pengutronix.de, fugang.duan@nxp.com Subject: [PATCH 1/1] ARM: dts: imx6sx: fix the pad QSPI1B_SCLK mux mode for uart3 Date: Thu, 3 Sep 2020 18:05:21 +0800 Message-Id: <20200903100521.10464-1-fugang.duan@nxp.com> X-Mailer: git-send-email 2.17.1 Content-Type: text/plain X-ClientProxiedBy: SG2PR03CA0132.apcprd03.prod.outlook.com (2603:1096:4:91::36) To AM8PR04MB7315.eurprd04.prod.outlook.com (2603:10a6:20b:1d4::7) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from 255.255.255.255 (255.255.255.255) by SG2PR03CA0132.apcprd03.prod.outlook.com (2603:1096:4:91::36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.9 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 0c92g24hfzrI7pT9xD5ldXWjX2qmlatLsFN9FbpykxAdGveFyJ76m97zokjqnkDwMjH+VzzuXVMoYgKIJIIrGBm0yM3r4ona2w+O8bL1ScT0PkliD8mTyHQ00/ePUdkKsDCjM6DRfIlCwTlhWdUs8MzbYqNdrpLcyhHJfo6D8QQVvjx+YRja0D4B+oUBY9Wn0d+xkaJDDemheShreGGPlHkRR1Dmrx8k9xYjE2dbF2nVROmmCEF7anEdLAHWkHLBPgsHydgxMEJf/otLKVskISyEESzU8ILFGM9Kv/KBphvoBXuwX4HraJH4+OpQvE79zhODZZaWSaK/6kpl5+tCahX7gO/YjVdJjmXeHVTBenkNJ06jQXFXQT4OyWRQFTZtdD7G2FOvBZo8kCOjU/fLxQs5SEGTp343sAa49IC+nGl6RsCx69GNq54Yl+nw61Q+mzxAnzfXaBPTNjS4Qf1GkYBtTIRe6R42ZNuO+NFfKTzNm9YojIaIbBk9A8+k/GVy31IopZEBc9O7pQcBPjxq3+q3WG7vGDWdtyNQpzmGGthtHZ0Uc/ZedXWu341OzND4ZIHZZPatdOnkiBLJ0cW7d2LBROkAKCCMbQczO5+GMOaSv2lstDmJCx+KnTiVIdkHmcKucekjYp+GBmz4cp23SA== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9d218dbf-7e80-4595-73d0-08d84ff2402f X-MS-Exchange-CrossTenant-AuthSource: AM8PR04MB7315.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Sep 2020 10:15:15.3393 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xfv5m+FXsZd1mu9J7/GUQMSiUPxjMkII0xI5Dj0/GM767F8v/PsXAArEMKj57U32VsqVXcPibEwMaE12escrxQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB6404 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Fugang Duan The pad QSPI1B_SCLK mux mode 0x1 is for function UART3_DTE_TX, correct the mux mode. Fixes: 743636f25f1d ("ARM: dts: imx: add pin function header for imx6sx") Signed-off-by: Fugang Duan --- arch/arm/boot/dts/imx6sx-pinfunc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h index 0b02c7e60c17..f4dc46207954 100644 --- a/arch/arm/boot/dts/imx6sx-pinfunc.h +++ b/arch/arm/boot/dts/imx6sx-pinfunc.h @@ -1026,7 +1026,7 @@ #define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0 #define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x01B4 0x04FC 0x0840 0x1 0x4 -#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x0 0x0 +#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x1 0x0 #define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1 #define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2 #define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1 -- 2.17.1